AN 960: JESD204C Intel® FPGA IP and ADI AD9081 MxFE* ADC Interoperability Report for Intel Agilex® 7 E-Tile Devices

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ID 709330
Date 3/27/2023
Public
Document Table of Contents
Document Table of Contents x
1. JESD204C Intel® FPGA IP and ADI AD9081 MxFE* ADC Interoperability Checkout Report for Intel Agilex® 7 E-Tile Devices
1. JESD204C Intel® FPGA IP and ADI AD9081 MxFE* ADC Interoperability Checkout Report for Intel Agilex® 7 E-Tile Devices x
1.1. Hardware and Software Requirements 1.2. Hardware Setup 1.3. System Description 1.4. Interoperability Methodology 1.5. JESD204C Intel® FPGA IP and ADC Configurations 1.6. Test Results 1.7. Test Result Comments 1.8. Document Revision History for AN 960: JESD204C Intel® FPGA IP and ADI AD9081 MxFE* ADC Interoperability Report for Intel Agilex® 7 E-Tile Devices 1.9. Appendix
1.2. Hardware Setup x
1.2.1. Switching Reference Clocks
1.2.1. Switching Reference Clocks x
1.2.1.1. Procedure
1.4. Interoperability Methodology x
1.4.1. Receiver Data Link Layer 1.4.2. Receiver Transport Layer (TL) 1.4.3. Deterministic Latency - Subclass 1 (DL)
1.4.1. Receiver Data Link Layer x
1.4.1.1. Sync Header Alignment (SHA) 1.4.1.2. Extended Multiblock Alignment (EMBA)
1. JESD204C Intel® FPGA IP and ADI AD9081 MxFE* ADC Interoperability Checkout Report for Intel Agilex® 7 E-Tile Devices

1.4.1. Receiver Data Link Layer

This test area covers the test cases for sync header alignment (SHA) and extended multiblock alignment (EMBA).

On link start up, after the receiver reset, the JESD204C Intel® FPGA IP starts looking for the sync header stream that is transmitted by the device. The following registers from data link layer are read during the test, written into log files, and verified for passing criteria through TCL scripts.


Section Content
Sync Header Alignment (SHA)
Extended Multiblock Alignment (EMBA)

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