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1.1. Hardware and Software Requirements
1.2. Hardware Setup
1.3. System Description
1.4. Interoperability Methodology
1.5. JESD204C Intel® FPGA IP and ADC Configurations
1.6. Test Results
1.7. Test Result Comments
1.8. Document Revision History for AN 960: JESD204C Intel® FPGA IP and ADI AD9081 MxFE* ADC Interoperability Report for Intel Agilex® 7 E-Tile Devices
1.9. Appendix
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1.9. Appendix
This report shows validation of the JESD204C Intel® FPGA IP and PHY electrical interface with the AD9081/9082 (R2 Silicon) device up to 24.75 Gbps for ADC. The complete configuration and hardware setup are shown to provide confidence in the interoperability and performance of the two devices.