AN 960: JESD204C Intel® FPGA IP and ADI AD9081 MxFE* ADC Interoperability Report for Intel Agilex® 7 E-Tile Devices

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ID 709330
Date 3/27/2023
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Document Table of Contents
Document Table of Contents x
1. JESD204C Intel® FPGA IP and ADI AD9081 MxFE* ADC Interoperability Checkout Report for Intel Agilex® 7 E-Tile Devices
1. JESD204C Intel® FPGA IP and ADI AD9081 MxFE* ADC Interoperability Checkout Report for Intel Agilex® 7 E-Tile Devices x
1.1. Hardware and Software Requirements 1.2. Hardware Setup 1.3. System Description 1.4. Interoperability Methodology 1.5. JESD204C Intel® FPGA IP and ADC Configurations 1.6. Test Results 1.7. Test Result Comments 1.8. Document Revision History for AN 960: JESD204C Intel® FPGA IP and ADI AD9081 MxFE* ADC Interoperability Report for Intel Agilex® 7 E-Tile Devices 1.9. Appendix
1.2. Hardware Setup x
1.2.1. Switching Reference Clocks
1.2.1. Switching Reference Clocks x
1.2.1.1. Procedure
1.4. Interoperability Methodology x
1.4.1. Receiver Data Link Layer 1.4.2. Receiver Transport Layer (TL) 1.4.3. Deterministic Latency - Subclass 1 (DL)
1.4.1. Receiver Data Link Layer x
1.4.1.1. Sync Header Alignment (SHA) 1.4.1.2. Extended Multiblock Alignment (EMBA)
1. JESD204C Intel® FPGA IP and ADI AD9081 MxFE* ADC Interoperability Checkout Report for Intel Agilex® 7 E-Tile Devices

1.4.2. Receiver Transport Layer (TL)

To check the data integrity of the payload data stream through the receiver (RX) JESD204C Intel® FPGA IP and transport layer, the ADC is configured to ramp/PRBS test pattern. The ADC is also set to operate with the same configuration as set in the JESD204C Intel® FPGA IP. The ramp/PRBS checker in the FPGA fabric checks the ramp/PRBS data integrity for one minute. The RX JESD204C Intel® FPGA IP register rx_err is polled continuously for zero value for one minute.

The figure below shows the conceptual test setup for data integrity checking.

Figure 4. Data Integrity Check Using Ramp/PRBS15 Checker
Table 3.  Transport Layer Test Cases
Test Case Objective Description Passing Criteria
TL.1 Check the transport layer mapping of the data channel using ramp test pattern. Data_mode is set to Ramp_mode.

The following signals are read through registers:

  • crc_err is read rx_err_status (0x60[14]).
  • jrx_patchk_data_error is read from the tst_err0 register.
  • crc_err should be low to pass.
  • jrx_patchk_data_error should be low.
TL.2 Check the transport layer mapping of the data channel using the PRBS15 test pattern. Data_mode is set to prbs_mode.

The following values are read from registers:

  • crc_err is read jrx_err_status (0x60[14]).
  • jrx_patchk_data_error is read from the tst_err0 register.
  • crc_err should be low to pass.
  • jrx_patchk_data_error should be low.
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