F-Tile HDMI Intel® FPGA IP Design Example User Guide

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ID 709314
Date 4/22/2022
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Document Table of Contents
Document Table of Contents x
1. HDMI Intel® FPGA IP Design Example Quick Start Guide for Intel® Agilex™ F-tile Devices 2. HDMI 2.1 Design Example (Support FRL = 1) 3. Document Revision History for the F-Tile HDMI Intel® FPGA IP Design Example User Guide
1. HDMI Intel® FPGA IP Design Example Quick Start Guide for Intel® Agilex™ F-tile Devices x
1.1. Directory Structure 1.2. Generating the Design 1.3. Simulating the Design 1.4. Compiling and Testing the Design
2. HDMI 2.1 Design Example (Support FRL = 1) x
2.1. Design Features 2.2. Hardware and Software Requirements 2.3. HDMI 2.1 RX-TX Retransmit Design Block Diagram 2.4. Design Parameters 2.5. Design Components 2.6. Design Software Flow 2.7. Clocking Scheme 2.8. Interface Signals 2.9. Hardware Setup 2.10. Simulation Testbench 2.11. Debugging Features
2.3. HDMI 2.1 RX-TX Retransmit Design Block Diagram x
2.3.1. Creating RX-Only or TX-Only Designs
2.4. Design Parameters x
2.4.1. IP Parameters 2.4.2. HDMI Intel® FPGA IP Design Example Parameters
2.5. Design Components x
2.5.1. HDMI TX Components 2.5.2. HDMI RX Components 2.5.3. Top-Level Common Blocks
2.5.1. HDMI TX Components x
2.5.1.1. TX PHY Adapter
2.5.1.1. TX PHY Adapter x
2.5.1.1.1. FRL
2.5.2. HDMI RX Components x
2.5.2.1. RX PHY Adapter
2.5.2.1. RX PHY Adapter x
2.5.2.1.1. FRL
2.11. Debugging Features x
2.11.1. Software Debug Message 2.11.2. SCDC Information from Sink Connected to TX 2.11.3. Clock Frequency Measurement
1. HDMI Intel® FPGA IP Design Example Quick Start Guide for Intel® Agilex™ F-tile Devices
2. HDMI 2.1 Design Example (Support FRL = 1)
3. Document Revision History for the F-Tile HDMI Intel® FPGA IP Design Example User Guide

2.5.1.1. TX PHY Adapter

To support HDMI, TX PMA Direct PHY is configured to 64 bits parallel data width. Due to the HDMI TX inter-lane skew requirement for HDMI 1.4, HDMI 2.0 and HDMI 2.1, certain HDMI data rate needs to be oversampled to 24 Gbps to meet the inter-lane skew. Due to the maximum system clock frequency of 900 Mhz, the TX PHY needs to be configured to 64 bits (32 bits PMA width with byte serializer turned on) which result in the PMA clock of 750 Mhz.

In the TX PMA Direct PHY architecture with the system PLL, a DCFIFO is required to clock the TX parallel data from the link speed clock (data rate/effective transceiver width) to the system clock (sys_clk_div2) domain.

Figure 10. 40 bits to 64 bits Converter

A 40 bits to 64 bits converter is designed with four 40 bits register to store the RX parallel data from the RX core. The first 64 bits data is outputted after the 3rd clock cycle. After that, 64 bits data is outputted at the next 5 consecutive clock cycles. The process is repeated for every 8-clock cycle.


Section Content
FRL

Level Two Title