F-Tile HDMI Intel® FPGA IP Design Example User Guide

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ID 709314
Date 4/22/2022
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Document Table of Contents
Document Table of Contents x
1. HDMI Intel® FPGA IP Design Example Quick Start Guide for Intel® Agilex™ F-tile Devices 2. HDMI 2.1 Design Example (Support FRL = 1) 3. Document Revision History for the F-Tile HDMI Intel® FPGA IP Design Example User Guide
1. HDMI Intel® FPGA IP Design Example Quick Start Guide for Intel® Agilex™ F-tile Devices x
1.1. Directory Structure 1.2. Generating the Design 1.3. Simulating the Design 1.4. Compiling and Testing the Design
2. HDMI 2.1 Design Example (Support FRL = 1) x
2.1. Design Features 2.2. Hardware and Software Requirements 2.3. HDMI 2.1 RX-TX Retransmit Design Block Diagram 2.4. Design Parameters 2.5. Design Components 2.6. Design Software Flow 2.7. Clocking Scheme 2.8. Interface Signals 2.9. Hardware Setup 2.10. Simulation Testbench 2.11. Debugging Features
2.3. HDMI 2.1 RX-TX Retransmit Design Block Diagram x
2.3.1. Creating RX-Only or TX-Only Designs
2.4. Design Parameters x
2.4.1. IP Parameters 2.4.2. HDMI Intel® FPGA IP Design Example Parameters
2.5. Design Components x
2.5.1. HDMI TX Components 2.5.2. HDMI RX Components 2.5.3. Top-Level Common Blocks
2.5.1. HDMI TX Components x
2.5.1.1. TX PHY Adapter
2.5.1.1. TX PHY Adapter x
2.5.1.1.1. FRL
2.5.2. HDMI RX Components x
2.5.2.1. RX PHY Adapter
2.5.2.1. RX PHY Adapter x
2.5.2.1.1. FRL
2.11. Debugging Features x
2.11.1. Software Debug Message 2.11.2. SCDC Information from Sink Connected to TX 2.11.3. Clock Frequency Measurement
1. HDMI Intel® FPGA IP Design Example Quick Start Guide for Intel® Agilex™ F-tile Devices
2. HDMI 2.1 Design Example (Support FRL = 1)
3. Document Revision History for the F-Tile HDMI Intel® FPGA IP Design Example User Guide

1.2. Generating the Design

Use the HDMI Intel® FPGA IP parameter editor in the Intel® Quartus® Prime software to generate the design examples.
Figure 3. Generating the Design Flow
  1. Create a project targeting Intel® Agilex™ F-tile device family and select the desired device.
  2. In the IP Catalog, locate and double-click HDMI Intel FPGA IP. The New IP Variant or New IP Variation window appears.
  3. Specify a top-level name for your custom IP variation. The parameter editor saves the IP variation settings in a file named <your_ip>.ip .
  4. Click OK. The parameter editor appears.
  5. On the IP tab, configure the desired parameters for both TX and RX.
  6. Support FRL is turned on by default to generate the HDMI 2.1 design example in FRL mode.
  7. On the Design Example tab, select Agilex HDMI RX-TX Retransmit.
  8. Select Simulation to generate the testbench, and select Synthesis to generate the hardware design example.
    You must select at least one of these options to generate the design example files. If you select both, the generation time is longer.
  9. For Generate File Format, select Verilog or VHDL.
  10. For Select Board, select the relevant development kit. You can change the target device using Change Target Device parameter if your board revision does not match the grade of the default targeted device. For Agilex FPGA Development Kit, the default device is AGIB027R31B1E2VR0.
  11. Click Generate Example Design.
Level Two Title