F-Tile HDMI Intel® FPGA IP Design Example User Guide

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ID 709314
Date 4/22/2022
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Document Table of Contents
Document Table of Contents x
1. HDMI Intel® FPGA IP Design Example Quick Start Guide for Intel® Agilex™ F-tile Devices 2. HDMI 2.1 Design Example (Support FRL = 1) 3. Document Revision History for the F-Tile HDMI Intel® FPGA IP Design Example User Guide
1. HDMI Intel® FPGA IP Design Example Quick Start Guide for Intel® Agilex™ F-tile Devices x
1.1. Directory Structure 1.2. Generating the Design 1.3. Simulating the Design 1.4. Compiling and Testing the Design
2. HDMI 2.1 Design Example (Support FRL = 1) x
2.1. Design Features 2.2. Hardware and Software Requirements 2.3. HDMI 2.1 RX-TX Retransmit Design Block Diagram 2.4. Design Parameters 2.5. Design Components 2.6. Design Software Flow 2.7. Clocking Scheme 2.8. Interface Signals 2.9. Hardware Setup 2.10. Simulation Testbench 2.11. Debugging Features
2.3. HDMI 2.1 RX-TX Retransmit Design Block Diagram x
2.3.1. Creating RX-Only or TX-Only Designs
2.4. Design Parameters x
2.4.1. IP Parameters 2.4.2. HDMI Intel® FPGA IP Design Example Parameters
2.5. Design Components x
2.5.1. HDMI TX Components 2.5.2. HDMI RX Components 2.5.3. Top-Level Common Blocks
2.5.1. HDMI TX Components x
2.5.1.1. TX PHY Adapter
2.5.1.1. TX PHY Adapter x
2.5.1.1.1. FRL
2.5.2. HDMI RX Components x
2.5.2.1. RX PHY Adapter
2.5.2.1. RX PHY Adapter x
2.5.2.1.1. FRL
2.11. Debugging Features x
2.11.1. Software Debug Message 2.11.2. SCDC Information from Sink Connected to TX 2.11.3. Clock Frequency Measurement
1. HDMI Intel® FPGA IP Design Example Quick Start Guide for Intel® Agilex™ F-tile Devices
2. HDMI 2.1 Design Example (Support FRL = 1)
3. Document Revision History for the F-Tile HDMI Intel® FPGA IP Design Example User Guide

3. Document Revision History for the F-Tile HDMI Intel® FPGA IP Design Example User Guide

Document Version Intel® Quartus® Prime Version IP Version Changes
2022.04.22 22.1 19.7.0
  • Renamed the document title from HDMI Intel® Agilex™ F-Tile FPGA IP Design Example User Guide to F-Tile HDMI Intel FPGA IP Design Example User Guide.
  • Updated Directory Structure for the Design Example figure.
  • Updated Generated RTL Files table with additional folder and file/subfolders.li
  • Updated Generated Simulation Files table with additional folder and file/subfolders.
  • Updated default device in steps in Generating the Design section.
  • Added figure title Design Compilation and Hardware Flow in Compiling and Testing the Design section.
  • Added additional steps in Compiling and Testing the Design section.
  • Updated data rate in HDMI 2.1 Design Example for Intel Agilex F-tile Devices table.
  • Updated features in Design Features section.
  • Updated example, revision and version details in Hardware section in Hardware and Software Requirements section.
  • Updated HDMI 2.1 RX-TX Retransmit Block Diagram figure.
  • Updated HDMI 2.1 RX-only Block Diagram figure.
  • Updated HDMI 2.1 TX-only Block Diagram figure.
  • Updated Target Development Kit details in Design Example Parameters for Devices table.
  • Added Module details in HDMI TX Top Components table.
  • Updated clock signals for FRL in RX PHY Adapter section.
  • Updated clock signals for FRL in TX PHY Adaptersection.
  • Updated Top-Level Common Blocks table with addtional modules.
  • Updated RX Path Initialization Flowchart table.
  • Updated Clocking Scheme Signals table with additional clocks.
  • Added additional signals under On-board Oscillator Signal and User Push Buttons and LEDs in Top-Level Signals table.
  • Added additional signals under Clock and Reset Signals and RX Transceiver and IOPLL Signals in HDMI RX Top-Level Signals table.
  • Added a separate section for RX Reconfiguration Management and addtional signals in HDMI RX Top-Level Signals table.
  • Added additional signals under Clock and Reset Signals, TX Transceiver and IOPLL Signals, TX Reconfiguration Management and Hotplug Detect Signals in HDMI TX Top-Level Signals table.
  • Added additinal signals in RX-TX Link Signals table.
2021.12.13 21.4 19.6.1 Initial release.
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