F-Tile HDMI Intel® FPGA IP Design Example User Guide

ID 709314
Date 4/22/2022
Public

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Document Table of Contents

1.1. Directory Structure

The directories contain the generated files for the HDMI Intel® FPGA IP design example.
Figure 2. Directory Structure for the Design Example
Table 1.  Generated RTL Files
Folders Files/Subfolders
common clock_crosser.v
dcfifo_inst.v
edge_detector.sv
fifo.ip
output_buf_i2c.ip
test_pattern_gen.v
mr_rate_detect.v
tpg_data.v
dr dr.ip
gxb gxb_rx.v
gxb_tx.v
gxb/rx_phy data_converter_64to40.v
rx_phy_3g.ip
rx_phy_6g.ip
rx_phy_8g.ip
rx_phy_10g.ip
rx_phy_12g.ip
rx_phy_5p940g.ip
gxb/tx_phy data_converter_40to64.v
tx_phy_3g.ip
tx_phy_6g.ip
tx_phy_8g.ip
tx_phy_10g.ip
tx_phy_12g.ip
tx_phy_5p940g.ip
gxb/sys_clk sys_clk.ip
hdmi_rx hdmi_rx.ip
hdmi_rx_top.v
Panasonic.hex
hdmi_tx hdmi_tx.ip
hdmi_tx_top.v
i2c_slave i2c_avl_mst_intf_gen.v
i2c_clk_cnt.v
i2c_condt_det.v
i2c_databuffer.v
i2c_rxshifter.v
i2c_slvfsm.v
i2c_spksupp.v
i2c_txout.v
i2c_txshifter.v
i2cslave_to_avlmm_bridge.v
pll pll_frl_rx.ip
pll_frl_tx.ip
pll_pixel.ip
pll_vidclk.ip
reconfig mr_rx_iopll_tmds/
mr_rxphy/
mr_tx_fpll/
altera_xcvr_functions.sv
mr_compare.sv
mr_rate_detect.v
mr_rx_rate_detect_top.v
mr_rx_rcfg_ctrl.v
mr_rx_reconfig.v
mr_tx_rate_detect_top.v
mr_tx_rcfg_ctrl.v
mr_tx_reconfig.v
rcfg_array_streamer_iopll.sv
rcfg_array_streamer_rxphy.sv
rcfg_array_streamer_rxphy_xn.sv
rcfg_array_streamer_txphy.sv
rcfg_array_streamer_txphy_xn.sv
rcfg_array_streamer_txpll.sv
rxtx_link altera_hdmi_hdr_infoframe.v
aux_mux.qsys
aux_retransmit.v
aux_src_gen.v
ext_aux_filter.v
rxtx_link.v
scfifo_vid.ip
sdc agx_hdmi2.sdc
jtag.sdc
Note: The folders mr_rx_iopll_tmds/, mr_rxphy/, mr_tx_fpll/ are not aplicable for this release. These folders will be available in the later release.
Table 2.  Generated Simulation FilesRefer to the Simulation Testbench section for more information.
Folders Files
aldec /aldec.do
/rivierapro_setup.tcl
mentor /mentor.do
/msim_setup.tcl
synopsys /vcs/filelist.f
/vcs/vcs_setup.sh
/vcs/vcs_sim.sh
/vcsmx/synopsys_sim_setup
/vcsmx/vcsmx_setup.sh
/vcsmx/vcsmx_sim.sh
xcelium /cds.lib
/hdl.var
/xcelium_setup.sh
/xcelium_sim.sh
<cds_libs folder>
common /modelsim_files.tcl
/riviera_files.tcl
/vcs_files.tcl
/ncsim_files.tcl
/vcsmx_files.tcl
/xcelium_files.tcl
hdmi_rx /hdmi_rx.ip
/Panasonic.hex
hdmi_tx /hdmi_tx.ip
Table 3.  Generated Software Files
Folders Files
tx_control_src
Note: The tx_control folder also contains duplicates of these files.
global.h
hdmi_rx.c
hdmi_rx.h
hdmi_tx.c
hdmi_tx.h
hdmi_tx_read_edid.c
hdmi_tx_read_edid.h
intel_fpga_i2c.c
intel_fpga_i2c.h
main.c
pio_read_write.c
pio_read_write.h