AN 952: Intel® Arria® 10 and Intel® Stratix® 10 HDMI 2.1 System Design Guidelines

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ID 709310
Date 6/21/2022
Public
Document Table of Contents
Document Table of Contents x
1. Terms and Acronyms 2. Introduction 3. Prerequisites and Scope 4. System Design Guidelines Requirements 5. HDMI 2.1 Compliance Test Specification 6. Future System Level Optimization 7. Document Revision History for AN 952: Intel® Arria® 10 and Intel® Stratix® 10 HDMI 2.1 System Design Guidelines
4. System Design Guidelines Requirements x
4.1. Enabling PCB panel design 4.2. PCB Best Practices 4.3. System Link Budgeting Recommendations
4.3. System Link Budgeting Recommendations x
4.3.1. FPGA TX Settings 4.3.2. FPGA RX Settings
4.3.2. FPGA RX Settings x
4.3.2.1. Intel® Stratix® 10-specific RX Feature
5. HDMI 2.1 Compliance Test Specification x
5.1. Protocol IP Compliance Test Specification 5.2. Electrical Compliance Test Specification 5.3. Performance and Cost Considerations
6. Future System Level Optimization x
6.1. Availability of Redrivers or Retimers 6.2. The Intel Agilex® Platform
1. Terms and Acronyms
2. Introduction
3. Prerequisites and Scope
4. System Design Guidelines Requirements
5. HDMI 2.1 Compliance Test Specification
6. Future System Level Optimization
7. Document Revision History for AN 952: Intel® Arria® 10 and Intel® Stratix® 10 HDMI 2.1 System Design Guidelines

4.3.2. FPGA RX Settings

You must use a redriver on the PCB panel to ensure compliance to RX CTS and HDMI 2.1 cable loss. Intel products do not support non-compliant cables. The equalization is dependent on overall system reach design; in a typical scenario, 16 dB is sufficient, while longer traces on larger PCB panels require higher equalization.

You can use flex cables instead of a large PCB panel for a better cost-to-performance ratio. Use link training methodology to evaluate if such cables match your setup. Validation setup uses generic jitter tolerance methodology to meet HDMI 2.1 CTS requirements.

Below is a summary of targeted loss calibration:
Table 7.  Targeted loss calibration
Insertion Loss : 20.11 dB
Spec Calibrated
Amplitude 800-1200 mV -
RJ 0.2 UI 1.31 ps 1.224 ps 0.12 UI
DJ 0.35 UI 29.2 ps - -
BUJ 0.15 UI 12.5 ps 12 ps 0.12 UI
SJ/PJ 0.1 UI 8.33 ps 9.33 ps 0.1 UI
Eye Height 100 mV - 97.1 mV
Eye Weight 29.17 ps - 31.5 ps

The jitter (BUJ) interpretation varies. Focus on the entire system level with all components account for 1 UI budget. HDMI.org provides WCM cable that shows the cable loss parameter. The stressed signal feeds into RX to establish jitter tolerance. The following table lists the recommended settings:

Table 8.  FPGA RX Recommended Settings
Component Intel® Arria® 10 FPGA Redriver

(TI DS125MB203)
Adaptation Mode Manual CTLE, TX FFE EQ DeEmp VOD
VGA Gain 2 - -
DC Gain 1 - -
AC Gain 3 Level4 Level 0-2

1

2

Vpp Amplitude - - 0.8

Do note that a 2 UI TX length at 6 Gbps at Test Point 1 is a mandate by HDMI 2.1 CTS.

All settings listed in this document are available in Intel® Quartus® Prime. You can update the settings to reflect the need of each design requirements as well as loss factor.

To mitigate variability in customer loss profiles:

  1. Isolate and confirm that the root cause is the transceiver link.
  2. Apply link tuning methodology.
  3. Refer TTK (transceiver toolkit):
    • Evaluate link stability and robustness by sweeping transceiver analog settings (for loss profiles beyond nominal cases).
    • Find the optimal RX analog settings with TTK.
    • Apply static values in the QSF file.

Section Content
Intel Stratix 10-specific RX Feature

Related Information
1 Intel recommends that you start with Level 0 to evaluate link stability. This setting depends on incoming TX Vpp including link setup. The larger the Vpp, the higher the level of deemphasis setting possible.
2 Refer to Performance and Cost Considerations.
Level Two Title