AN 952: Intel® Arria® 10 and Intel® Stratix® 10 HDMI 2.1 System Design Guidelines

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ID 709310
Date 6/21/2022
Public
Document Table of Contents
Document Table of Contents x
1. Terms and Acronyms 2. Introduction 3. Prerequisites and Scope 4. System Design Guidelines Requirements 5. HDMI 2.1 Compliance Test Specification 6. Future System Level Optimization 7. Document Revision History for AN 952: Intel® Arria® 10 and Intel® Stratix® 10 HDMI 2.1 System Design Guidelines
4. System Design Guidelines Requirements x
4.1. Enabling PCB panel design 4.2. PCB Best Practices 4.3. System Link Budgeting Recommendations
4.3. System Link Budgeting Recommendations x
4.3.1. FPGA TX Settings 4.3.2. FPGA RX Settings
4.3.2. FPGA RX Settings x
4.3.2.1. Intel® Stratix® 10-specific RX Feature
5. HDMI 2.1 Compliance Test Specification x
5.1. Protocol IP Compliance Test Specification 5.2. Electrical Compliance Test Specification 5.3. Performance and Cost Considerations
6. Future System Level Optimization x
6.1. Availability of Redrivers or Retimers 6.2. The Intel Agilex® Platform
1. Terms and Acronyms
2. Introduction
3. Prerequisites and Scope
4. System Design Guidelines Requirements
5. HDMI 2.1 Compliance Test Specification
6. Future System Level Optimization
7. Document Revision History for AN 952: Intel® Arria® 10 and Intel® Stratix® 10 HDMI 2.1 System Design Guidelines

4.3.2.1. Intel® Stratix® 10-specific RX Feature

Intel® Stratix® 10 supports RX Auto Adaptation capability. This mode does not require you to set RX values manually; rather, Intel® Stratix® 10 provides you with the optimized settings in real time. To enable this mode, compile your design with Adaptation mode set to Auto. Refer to the Intel Stratix 10 Transceiver User Guide for more details.

This reference design uses a TI Redriver with settings similar to those described in Table: FPGA RX Recommended Settings and 8 dB compensation to meet CTS cable loss requirements.

The cables you use must meet HDMI 2.1 specifications. Backplanes are not part of CTS certification. Therefore, you need to ensure your design’s overall system link loss profiles are within CTS targets.

The table below outlines the Worsecase Cable Model used in characterization to modulate with the SJ component:

Table 9.   Intel® Stratix® 10 Worsecase Cable Model Target Compensation
Protocol or Sub-protocol Data Rate (Mbps) VCCR/T_GXB Voltage Level (V) Test Channel Insertion Loss (dB) Redriver Settings
EQ Gain EQ Output VOD EQ Output DE
HDMI_12000_FRL 12,000 1.03 20.1832 8.7 dB at 5 GHz 0.8 Vpp 0 dB
Note: EQ, VOD, and DE denote equalizer, output differential voltage, and de-emphasis, respectively.

As a result, you need to set 8 dB equalization at 12 Gbps to meet HDMI 2.1 CTS requirements. Jitter tolerance on HDMI 2.1 Gbps is met.

Figure 4. Jitter Tolerance for HDMI_12000_FRL (1.03-VCCR/T_GXB Voltage Level)
Note: Measurements at lower jitter frequencies are constrained by the measurement setup. Measurements are obtained without a clock recovery unit to track lower frequency jitter components.
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