AN 952: Intel® Arria® 10 and Intel® Stratix® 10 HDMI 2.1 System Design Guidelines

Download PDF
ID 709310
Date 6/21/2022
Public
Document Table of Contents
Document Table of Contents x
1. Terms and Acronyms 2. Introduction 3. Prerequisites and Scope 4. System Design Guidelines Requirements 5. HDMI 2.1 Compliance Test Specification 6. Future System Level Optimization 7. Document Revision History for AN 952: Intel® Arria® 10 and Intel® Stratix® 10 HDMI 2.1 System Design Guidelines
4. System Design Guidelines Requirements x
4.1. Enabling PCB panel design 4.2. PCB Best Practices 4.3. System Link Budgeting Recommendations
4.3. System Link Budgeting Recommendations x
4.3.1. FPGA TX Settings 4.3.2. FPGA RX Settings
4.3.2. FPGA RX Settings x
4.3.2.1. Intel® Stratix® 10-specific RX Feature
5. HDMI 2.1 Compliance Test Specification x
5.1. Protocol IP Compliance Test Specification 5.2. Electrical Compliance Test Specification 5.3. Performance and Cost Considerations
6. Future System Level Optimization x
6.1. Availability of Redrivers or Retimers 6.2. The Intel Agilex® Platform
1. Terms and Acronyms
2. Introduction
3. Prerequisites and Scope
4. System Design Guidelines Requirements
5. HDMI 2.1 Compliance Test Specification
6. Future System Level Optimization
7. Document Revision History for AN 952: Intel® Arria® 10 and Intel® Stratix® 10 HDMI 2.1 System Design Guidelines

5.3. Performance and Cost Considerations

  1. Intel recommends that you enable TX FFE to ensure better interoperability among various HDMI 2.1 devices. However, RX jitter tolerance does not account for FFE usage.
  2. You can increase the performance of RX equalization and reduce FPGA dependency by utilizing redrivers or retimers that can compensate for higher loss profiles.
  3. Although using external redrivers or retimers can help your design meet CTS compliance, you must ensure that the settings are able to meet the proprietary loss profile setup.
    Note: The electrical validation optimization in this document does not cover non-Intel devices. If your profile setup is significantly different from what is shown here, use Link Tuning method to verify link integrity.
  4. For PCB designs that do not require Intel® Quartus® Prime compilation, you can refer to Channel Placement Tools (CPTs) specific to Intel® Arria® 10 or Intel® Stratix® 10, which allow you to allocate link topology by designated pinouts.
Level Two Title