4.2. PCB Best Practice
Outline below are list of applicable generic guidelines albeit not mandatory.
- Power (VDD) and ground (GND) pins must connect to corresponding power planes of the printed circuit board directly without passing through any resistor.
- You can minimize the thickness of the PCB dielectric layer so that the VDD and GND planes create low inductance paths.
- One low-ESR 0.1uF decoupling capacitor must mount at each VDD pin. Capacitors of smaller body size, for example 0402 package, is preferable as the insertion loss is lower. Place the capacitor closest to the VDD pin.
- Incorporate one capacitor with capacitance in the range of 4.7uF to 10uF in the power supply decoupling. You can use an ultra-low ESR ceramic. This capacitor can be placed further away from the FPGA than the 0.1uF VDD decoupling capacitors.
In addition to the list above, below are some guidelines on the PCB trace design.
- Route the high-speed TMDS traces on the top layer to avoid the use of vias (and the introduction of their inductances). This allows for clean interconnects from the HDMI connectors to the redriver inputs and outputs. It is important to match the electrical length of these high-speed traces to minimize both inter-pair and intra-pair skew (Refer to HDMI 2.1 CTS requirements for the measurement).
- Place a solid ground plane next to the high-speed single layer to establish controlled impedance (targetted Z) for transmission link interconnects and provides a better low–inductance path for the return current flow.
- Route slower control signals on the bottom layer to allows for greater flexibility as these signal links usually have margin to tolerate discontinuities such as vias thus higher insertion loss. Separate the signals with low voltage swing and single ended types from high speed differential pairs with larger (3x) spacing to minimize attenuation.
- Placing a power plane next to the ground plane creates an additional high-frequency bypass capacitance.
- If an additional supply voltage plane or signal layer is needed, add a second power/ground plane system to the stack to keep symmetry. This makes the stack mechanically stable and prevents it from warping. You can place the power and ground plane of each power system closer together, thus increasing the high frequency bypass capacitance significantly.
HDMI 2.1 supports the PCA (power over cable assembly). Evaluate the voltage drop on the 5V rail at both TX and RX. In general, the widening traces for 5V rail can tolerate higher current load since nominal voltage remains at 5V.
Evaluate the HDMI connector footprint carefully to ensure you use compliant connectors. Strap the Ground pins to the nearest ground plane and do not leave the pins dangling. A good ground reference is critical to have the desired impedance control.
Note: If there is significant change in Loss Profile, Intel recommends to simulate on Advanced Link Analyzer (ALA) for optimized TX/RX settings.