AN 952: Intel® Arria® 10 HDMI 2.1 System Design Guidelines

Download PDF
ID 709310
Date 6/29/2021
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents
Document Table of Contents x
1. Terms and Acronyms 2. Introduction 3. Scope of System Design Guidelines 4. System Design Guide Requirements 5. HDMI 2.1 Compliance Test Specification 6. Future System Level Optimization 7. Document Revision History for AN 952: Intel Arria 10 HDMI 2.1 System Design Guidelines
4. System Design Guide Requirements x
4.1. Enabling PCB panel design 4.2. PCB Best Practice 4.3. System Link Budgeting Recommendation
4.3. System Link Budgeting Recommendation x
4.3.1. FPGA TX Settings 4.3.2. FPGA RX Settings
5. HDMI 2.1 Compliance Test Specification x
5.1. Protocol IP Compliance Test Specification 5.2. Electrical Compliance Test Specification 5.3. Gaps and Resolution
6. Future System Level Optimization x
6.1. Availability of Redrivers/Retimers 6.2. Agilex Platform
1. Terms and Acronyms
2. Introduction
3. Scope of System Design Guidelines
4. System Design Guide Requirements
5. HDMI 2.1 Compliance Test Specification
6. Future System Level Optimization
7. Document Revision History for AN 952: Intel Arria 10 HDMI 2.1 System Design Guidelines

5.3. Gaps and Resolution

  1. TX FFE enabling is recommended to ensure better interoperability among various HDMI 2.1 devices.
  2. RX Equalization performance increases with better redrivers or retimers. Redrivers that are capable to compensate higher loss profile will reduce FPGA dependency.
  3. While external redrivers/retimers are recommended to meet CTS compliance, you must ensure these settings are able to meet the proprietary loss profile setup.
    Note: If the profile setup is significantly different from this document, you can apply Link Tuning method to verify link integrity. External devices (not part of Intel) is excluded from Electrical validation optimization and coverage.
Level Two Title