AN 952: Intel® Arria® 10 HDMI 2.1 System Design Guidelines

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ID 709310
Date 6/29/2021
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Document Table of Contents
Document Table of Contents x
1. Terms and Acronyms 2. Introduction 3. Scope of System Design Guidelines 4. System Design Guide Requirements 5. HDMI 2.1 Compliance Test Specification 6. Future System Level Optimization 7. Document Revision History for AN 952: Intel Arria 10 HDMI 2.1 System Design Guidelines
4. System Design Guide Requirements x
4.1. Enabling PCB panel design 4.2. PCB Best Practice 4.3. System Link Budgeting Recommendation
4.3. System Link Budgeting Recommendation x
4.3.1. FPGA TX Settings 4.3.2. FPGA RX Settings
5. HDMI 2.1 Compliance Test Specification x
5.1. Protocol IP Compliance Test Specification 5.2. Electrical Compliance Test Specification 5.3. Gaps and Resolution
6. Future System Level Optimization x
6.1. Availability of Redrivers/Retimers 6.2. Agilex Platform
1. Terms and Acronyms
2. Introduction
3. Scope of System Design Guidelines
4. System Design Guide Requirements
5. HDMI 2.1 Compliance Test Specification
6. Future System Level Optimization
7. Document Revision History for AN 952: Intel Arria 10 HDMI 2.1 System Design Guidelines

4.3.2. FPGA RX Settings

You must use a redriver on the PCB panel to meet the compliance for RX CTS and HDMI 2.1 cable loss. Non-compliant cables are not supported. The equalization is dependent on overall system reach design. In a typical scenario, 16dB is sufficient. However, higher values will be required when you use longer traces on larger PCB panels.

You can utilize flex cables instead of a large PCB panel for better cost to performance benefit. You need to apply link training methodology to evaluate if such cable can apply in your setup. Validation setup uses generic jitter tolerance methodology to meet HDMI 2.1 CTS requirement.

Below is a summary of targeted loss calibration:
Table 7.  Targeted loss calibration
Insertion Loss : 20.11 dB
Spec Calibrated
Amplitude 800-1200 mV -
Rj 0.2UI 1.31ps 1.224ps 0.12UI
Dj 0.35UI 29.2ps - -
BUj 0.15UI 12.5ps 12ps 0.12UI
SJ/PJ 0.1UI 8.33ps 9.33ps 0.1UI
Eye Height 100 mV - 97.1 mV
Eye Weight 29.17ps - 31.5ps

The jitter (BUJ) interpretation varies, you must focus on entire system level with all components account for 1 UI budget. The cable loss parameter is reflected by WCM cable provided by HDMI.org. The stressed signal feeds into RX to establish jitter tolerance. Settings required are listed below:

Table 8.  FPGA RX Recommended Settings
RX Settings
Component Intel® Arria® 10 FPGA Redriver

(TI DS125MB203)
Adaptation Mode Manual CTLE, TX FFE EQ DeEmp VOD
VGA Gain 2 - -
DC Gain 1 - -
AC Gain 3 Level4 Level 0-2

1

2

Vpp Amplitude - - 0.8

Do note TX length matching to 2UI at 6 Gbps at Test Point 1 is a mandate by HDMI 2.1 CTS.

All settings listed in this document shall be available in Intel® Quartus® Prime. You can update the settings to reflect the need per each design requirements as well as loss factor.

To mitigate variability in customer loss profiles:
  1. Isolate and confirm root cause is towards transceiver link.
  2. Apply link tuning methodology.
  3. Refer TTK (transceiver toolkit):
    • Evaluate link stability and robustness by sweeping transceiver analog settings (for loss profiles beyond nominal cases).
    • Find the optimal RX analog settings with TTK.
    • Apply static values in the QSF file.
Related Information
1 Intel recommends to start with Level0 to evaluate link stability. This setting depends on incoming TX Vpp including link setup. The larger Vpp, the higher the level of deemphasis setting possible.
2 Refer to Gaps and Resolution.
Level Two Title