AN 952: Intel® Arria® 10 HDMI 2.1 System Design Guidelines

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ID 709310
Date 6/29/2021
Public

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Document Table of Contents
Document Table of Contents x
1. Terms and Acronyms 2. Introduction 3. Scope of System Design Guidelines 4. System Design Guide Requirements 5. HDMI 2.1 Compliance Test Specification 6. Future System Level Optimization 7. Document Revision History for AN 952: Intel Arria 10 HDMI 2.1 System Design Guidelines
4. System Design Guide Requirements x
4.1. Enabling PCB panel design 4.2. PCB Best Practice 4.3. System Link Budgeting Recommendation
4.3. System Link Budgeting Recommendation x
4.3.1. FPGA TX Settings 4.3.2. FPGA RX Settings
5. HDMI 2.1 Compliance Test Specification x
5.1. Protocol IP Compliance Test Specification 5.2. Electrical Compliance Test Specification 5.3. Gaps and Resolution
6. Future System Level Optimization x
6.1. Availability of Redrivers/Retimers 6.2. Agilex Platform
1. Terms and Acronyms
2. Introduction
3. Scope of System Design Guidelines
4. System Design Guide Requirements
5. HDMI 2.1 Compliance Test Specification
6. Future System Level Optimization
7. Document Revision History for AN 952: Intel Arria 10 HDMI 2.1 System Design Guidelines

6.2. Agilex Platform

The card design for Intel® Arria® 10 family works on a typical level shifters from 1.8V up to 3.3V. However, to support future (and to extended timeframe for portability) Agilex family, the daughtercard level shifter of 1.0V is suitable on GPIO (general purpose IO).

Intel recommends to have DDC lines with proper pullup termination; the signals require mitigating voltage drop along the compliant cables.

Please contact Intel Support for guidance on Agilex system level enabling.

Level Two Title