4.3.1. FPGA TX Settings
TX on FPGA with below settings is recommended. Both FPLL and ATXPLL applies, generally ATX PLL has a slightly better margin compared to FPLL, although this may not be a dominant factor for Intel® Arria® 10.
| Item | Value |
| Vod output swing ctrl | 30 |
| Pre emp sign 1st post tap | Fir post 1t neg |
| Pre emp sign 2nd post tap | Fir post 2t neg |
| Pre emp switching ctrl 1st post tap | 5 |
| Pre emp switching ctrl 2nd post tap | 0 |
| Pre emp sign pre tap 1t | Fir pre 1t post |
| Pre emp sign pre tap 2t | Fir pre 2t neg |
| Pre emp switching ctrl pre tap 1t | 0 |
| Pre emp switching ctrl pre tap 2t | 0 |
| Slew rate ctrl | Slew r5 |
TX slew rate is set to r5 to ensure all 4 data channels (TMDS has 3 data channel and 1 clock) is within bonding requirements of 2UI at Test Point 1 (TP1) to meet inter-lane skew requirements.
TX redriver setting is dependent on PCB design profile. Intel recommends to keep VOD setting at 1.0 at the TX redriver. Any lower setting can cause more signal degradation.