1G/2.5G/5G/10G Multi-rate Ethernet PHY Intel® Stratix® 10 FPGA IP User Guide

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ID 683876
Date 11/15/2021
Public
Document Table of Contents
Document Table of Contents x
1. About the 1G/2.5G/5G/10G Multi-rate Ethernet PHY Intel® FPGA IP Core 2. Getting Started 3. Parameter Settings 4. Functional Description 5. Configuration Registers 6. Interface Signals 7. 1G/2.5G/5G/10G Multi-rate Ethernet PHY Intel® Stratix® 10 FPGA IP User Guide Archives A. Document Revision History for the 1G/2.5G/5G/10G Multi-rate Ethernet PHY Intel® Stratix® 10 FPGA IP User Guide
1. About the 1G/2.5G/5G/10G Multi-rate Ethernet PHY Intel® FPGA IP Core x
1.1. Features 1.2. Device Family Support 1.3. Device Speed Grade Support 1.4. Resource Utilization 1.5. Release Information
2. Getting Started x
2.1. Installing and Licensing Intel® FPGA IP Cores 2.2. Specifying the IP Core Parameters and Options 2.3. Generated File Structure 2.4. Integrating Your IP Core in Your Design
2.1. Installing and Licensing Intel® FPGA IP Cores x
2.1.1. Intel® FPGA IP Evaluation Mode
2.4. Integrating Your IP Core in Your Design x
2.4.1. Pin Assignments 2.4.2. Adding the Transceiver PLL 2.4.3. Adding the Intel® Stratix® 10 Transceiver PHY Reset Controller
4. Functional Description x
4.1. Clocking and Reset Sequence 4.2. Timing Constraints 4.3. Switching Operation Speed
5. Configuration Registers x
5.1. Register Map 5.2. Register Definitions
6. Interface Signals x
6.1. Clock and Reset Signals 6.2. Transceiver Mode and Operating Speed Signals 6.3. Serial Interface Signals 6.4. GMII Signals 6.5. XGMII Signals 6.6. Avalon® -MM Interface Signals 6.7. Transceiver Status and Reconfiguration Signals 6.8. Status Signals
1. About the 1G/2.5G/5G/10G Multi-rate Ethernet PHY Intel® FPGA IP Core
2. Getting Started
3. Parameter Settings
4. Functional Description
5. Configuration Registers
6. Interface Signals
7. 1G/2.5G/5G/10G Multi-rate Ethernet PHY Intel® Stratix® 10 FPGA IP User Guide Archives
A. Document Revision History for the 1G/2.5G/5G/10G Multi-rate Ethernet PHY Intel® Stratix® 10 FPGA IP User Guide

6.5. XGMII Signals

The XGMII supports 10GbE at 156.25 MHz.

Table 20.  XGMII Signals
Signal Name Direction Width Description PHY Configurations
TX XGMII signals — synchronous to xgmii_tx_coreclkin
xgmii_tx_data Input 64, 32 TX data from the MAC. The MAC sends the data in the following order: bits [7:0], bits [15:8], bit [23:16], and so on.
The width is:
  • 64 bits for 1G/2.5G/10G (MGBASE-T) configurations.
  • 32 bits for 10M/100M/1G/2.5G/5G/10G (USXGMII) configurations.
  • 1G/2.5G/10G (MGBASE-T)
  • 10M/100M/1G/2.5G/10G (MGBASE-T)
  • 10M/100M/1G/2.5G/5G/10G (USXGMII)
xgmii_tx_control Input 8, 4 TX control from the MAC. The xgmii_tx_control bit corresponds to the xgmii_tx_data bits. For example, xgmii_tx_control[0] corresponds to xgmii_tx_data[7:0], xgmii_tx_control[1] corresponds to xgmii_tx_data[15:8], and so on.
The width is:
  • 8 bits for 1G/2.5G/10G (MGBASE-T) configurations.
  • 4 bits for 10M/100M/1G/2.5G/5G/10G (USXGMII) configurations.
xgmii_tx_valid Input 1 Indicates valid data on xgmii_tx_control and xgmii_tx_data from the MAC.
Your logic/MAC must toggle the valid data as shown below:
Speed Toggle Rate
10M Asserted once every 1000 clock cycles
100M Asserted once every 100 clock cycles
1G Asserted once every 10 clock cycles
2.5G Asserted once every 4 clock cycles
5G Asserted once every 2 clock cycles
10G Asserted on every clock cycle
10M/100M/1G/2.5G/5G/10G (USXGMII)
xgmii_tx_latency Output 16, 24 The latency of the PHY excluding the PMA block on the TX datapath:
  • Bits [15:10] and [23:10]: The number of clock cycles.
  • Bits [9:0]: The fractional number of clock cycles.

The width is:

  • 16 bits for 1G/2.5G/10G (MGBASE-T) with IEEE 1588 configurations.
  • 24 bits for 10M/100M/1G/2.5G/5G/10G (USXGMII) configurations.

This signal is available when only the Enable IEEE 1588 Precision Time Protocol parameter is selected.

Note: For USXGMII configuration, the latency value may be unstable for the first three transmitted packets times (at least 64 bytes). You should not use the latency value within this period.
  • 1G/2.5G/10G (MGBASE-T) with IEEE 1588v2 feature
  • 10M/100M/1G/2.5G/5G/10G (USXGMII)
RX XGMII signals — synchronous to xgmii_rx_coreclkin
xgmii_rx_data Output 64, 32

RX data to the MAC. The PHY sends the data in the following order: bits [7:0], bits [15:8], bit [23:16], and so on.

The width is:
  • 64 bits for 1G/2.5G/10G (MGBASE-T) configurations.
  • 32 bits for 10M/100M/1G/2.5G/5G/10G (USXGMII) configurations.
  • 1G/2.5G/10G (MGBASE-T)
  • 10M/100M/1G/2.5G/10G (MGBASE-T)
  • 10M/100M/1G/2.5G/5G/10G (USXGMII)
xgmii_rx_control Output 8, 4 RX control to the MAC. The xgmii_rx_control bit corresponds to the xgmii_rx_data bits. For example, xgmii_rx_control[0] corresponds to xgmii_rx_data[7:0], xgmii_rx_control[1] corresponds to xgmii_rx_data[15:8], and so on.
The width is:
  • 8 bits for 1G/2.5G/10G (MGBASE-T) configurations.
  • 4 bits for 10M/100M/1G/2.5G/5G/10G (USXGMII) configurations.
xgmii_rx_valid Output 1 Indicates valid data on xgmii_rx_control and xgmii_rx_data from the MAC.
The toggle rate from the PHY is shown in the table below.
Speed Toggle Rate
10M Asserted once every 1000 clock cycles
100M Asserted once every 100 clock cycles
1G Asserted once every 10 clock cycles
2.5G Asserted once every 4 clock cycles
5G Asserted once every 2 clock cycles
10G Asserted on every clock cycle
Note: The toggle rate may vary when the start of a packet is received or when rate match occurs inside the PHY. You should not expect the valid data pattern to be fixed.
10M/100M/1G/2.5G/5G/10G (USXGMII)
xgmii_rx_latency Output 16, 24 The latency of the PHY excluding the PMA block on the TX datapath:
  • Bits [15:10]: The number of clock cycles.
  • Bits [9:0]: The fractional number of clock cycles.

The width is:

  • 16 bits for 1G/2.5G/10G (MGBASE-T) with IEEE 1588 configurations.
  • 24 bits for 10M/100M/1G/2.5G/5G/10G (USXGMII) configurations.

This signal is available when only the Enable IEEE 1588 Precision Time Protocol parameter is selected.

Note: For USXGMII configuration, the latency value may be unstable for the first three transmitted packets times (at least 64 bytes). You should not use the latency value within this period.
  • 1G/2.5G/10G (MGBASE-T) with IEEE 1588v2 feature
  • 10M/100M/1G/2.5G/5G/10G (USXGMII)
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