1G/2.5G/5G/10G Multi-rate Ethernet PHY Intel® Stratix® 10 FPGA IP User Guide

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ID 683876
Date 11/15/2021
Public
Document Table of Contents
Document Table of Contents x
1. About the 1G/2.5G/5G/10G Multi-rate Ethernet PHY Intel® FPGA IP Core 2. Getting Started 3. Parameter Settings 4. Functional Description 5. Configuration Registers 6. Interface Signals 7. 1G/2.5G/5G/10G Multi-rate Ethernet PHY Intel® Stratix® 10 FPGA IP User Guide Archives A. Document Revision History for the 1G/2.5G/5G/10G Multi-rate Ethernet PHY Intel® Stratix® 10 FPGA IP User Guide
1. About the 1G/2.5G/5G/10G Multi-rate Ethernet PHY Intel® FPGA IP Core x
1.1. Features 1.2. Device Family Support 1.3. Device Speed Grade Support 1.4. Resource Utilization 1.5. Release Information
2. Getting Started x
2.1. Installing and Licensing Intel® FPGA IP Cores 2.2. Specifying the IP Core Parameters and Options 2.3. Generated File Structure 2.4. Integrating Your IP Core in Your Design
2.1. Installing and Licensing Intel® FPGA IP Cores x
2.1.1. Intel® FPGA IP Evaluation Mode
2.4. Integrating Your IP Core in Your Design x
2.4.1. Pin Assignments 2.4.2. Adding the Transceiver PLL 2.4.3. Adding the Intel® Stratix® 10 Transceiver PHY Reset Controller
4. Functional Description x
4.1. Clocking and Reset Sequence 4.2. Timing Constraints 4.3. Switching Operation Speed
5. Configuration Registers x
5.1. Register Map 5.2. Register Definitions
6. Interface Signals x
6.1. Clock and Reset Signals 6.2. Transceiver Mode and Operating Speed Signals 6.3. Serial Interface Signals 6.4. GMII Signals 6.5. XGMII Signals 6.6. Avalon® -MM Interface Signals 6.7. Transceiver Status and Reconfiguration Signals 6.8. Status Signals
1. About the 1G/2.5G/5G/10G Multi-rate Ethernet PHY Intel® FPGA IP Core
2. Getting Started
3. Parameter Settings
4. Functional Description
5. Configuration Registers
6. Interface Signals
7. 1G/2.5G/5G/10G Multi-rate Ethernet PHY Intel® Stratix® 10 FPGA IP User Guide Archives
A. Document Revision History for the 1G/2.5G/5G/10G Multi-rate Ethernet PHY Intel® Stratix® 10 FPGA IP User Guide

4.3. Switching Operation Speed

Table 12.  Supported Operating Speed
PHY Configurations Features 10M 100M 1G 2.5G 5G 10G
2.5G Protocol — — — 1000BASE-X at 2.5x — —
Transceiver Data Rate — — — 3.125 Gbps — —
MAC Interface — — — 16-bit GMII @ 156.25 MHz — —
10M/100M/1G/2.5G Protocol SGMII

100x data replication

 SGMII

10x data replication

 1000BASE-X / SGMII 1000BASE-X at 2.5x — —
Transceiver Data Rate 1.25 Gbps 1.25 Gbps 1.25 Gbps 3.125 Gbps — —
MAC Interface 16-bit GMII @ 62.5 MHz 16-bit GMII @ 62.5 MHz 16-bit GMII @ 62.5 MHz 16-bit GMII @ 156.25 MHz — —
10M/100M/1G/2.5G/10G (MGBASE-T) Protocol SGMII SGMII

10x data replication

 1000BASE-X / SGMII 1000BASE-X at 2.5x — 10GBASE-R
Transceiver Data Rate 1.25 Gbps 1.25 Gbps 1.25 Gbps 3.125 Gbps — 10.3125 Gbps
MAC Interface 16-bit GMII @ 62.5 MHz 16-bit GMII @ 62.5 MHz 16-bit GMII @ 62.5 MHz 16-bit GMII @ 156.25 MHz — 64-bit XGMII @ 156.25 MHz
10M/100M/1G/2.5G/5G/10G (USXGMII) Protocol 10GBASE-R

1000x data replication

 10GBASE-R

100x data replication

 10GBASE-R

10x data replication

 10GBASE-R

4x data replication

 10GBASE-R

2x data replication

 10GBASE-R

No data replication
Transceiver Data Rate1 10.3125 Gbps 10.3125 Gbps 10.3125 Gbps 10.3125 Gbps 10.3125 Gbps 10.3125 Gbps
MAC Interface 32-bit XGMII @ 312.5 MHz 32-bit XGMII @ 312.5 MHz 32-bit XGMII @ 312.5 MHz 32-bit XGMII @ 312.5 MHz 32-bit XGMII @ 312.5 MHz 32-bit XGMII @ 312.5 MHz
You can change the PHY speed using the reconfiguration block in the MAC+PHY example design.
  1. Initiates the speed change by writing to the corresponding register of the reconfiguration block.2
  2. The reconfiguration block performs the following steps:
    1. Sets the xcvr_mode signal of the 1G/2.5G/5G/10G Multi-rate Ethernet PHY Intel® FPGA IP core to the requested speed.
    2. Reads the generated .mif file for the configuration settings and configures the transceiver accordingly.
    3. Selects the corresponding transceiver PLL.
    4. Triggers the transceiver recalibration.
  3. The reconfiguration block triggers the PHY reset through the transceiver reset controller.
Related Information
1 With oversampling for lower data rates.
2 You can change the speed within SGMII (10M/100M/1G) and USXGMII (10M/100M/1G/2.5G/5G/10G) through CSR. It doesn't require reconfiguration block.
Level Two Title