1G/2.5G/5G/10G Multi-rate Ethernet PHY Intel® Stratix® 10 FPGA IP User Guide

ID 683876
Date 11/15/2021
Public
Document Table of Contents

5.1. Register Map

You can access the 16-bit/32-bit configuration registers 3 via the Avalon® -MM interface.
Table 13.  Register Map Overview
Address Range Usage Register Width Configuration
0x00–0x1F 1000BASE-X/SGMII 16 2.5G, 1G/2.5G, 10M/100M/1G/2.5G, 10M/100M/1G/2.5G/10G (MGBASE-T), 1G/2.5G/10G (MGBASE-T)
0x400–0x41F USXGMII 32 10M/100M/1G/2.5G/5G/10G (USXGMII)
0x461 Serial Loopback 32 10M/100M/1G/2.5G/5G/10G (USXGMII)
3 These registers are identical to the Intel® Arria® 10 variation of 1G/2.5G/5G/10G Multi-rate Ethernet PHY Intel® FPGA IP core.