1G/2.5G/5G/10G Multi-rate Ethernet PHY Intel® Stratix® 10 FPGA IP User Guide

Download PDF
ID 683876
Date 11/15/2021
Public
Document Table of Contents
Document Table of Contents x
1. About the 1G/2.5G/5G/10G Multi-rate Ethernet PHY Intel® FPGA IP Core 2. Getting Started 3. Parameter Settings 4. Functional Description 5. Configuration Registers 6. Interface Signals 7. 1G/2.5G/5G/10G Multi-rate Ethernet PHY Intel® Stratix® 10 FPGA IP User Guide Archives A. Document Revision History for the 1G/2.5G/5G/10G Multi-rate Ethernet PHY Intel® Stratix® 10 FPGA IP User Guide
1. About the 1G/2.5G/5G/10G Multi-rate Ethernet PHY Intel® FPGA IP Core x
1.1. Features 1.2. Device Family Support 1.3. Device Speed Grade Support 1.4. Resource Utilization 1.5. Release Information
2. Getting Started x
2.1. Installing and Licensing Intel® FPGA IP Cores 2.2. Specifying the IP Core Parameters and Options 2.3. Generated File Structure 2.4. Integrating Your IP Core in Your Design
2.1. Installing and Licensing Intel® FPGA IP Cores x
2.1.1. Intel® FPGA IP Evaluation Mode
2.4. Integrating Your IP Core in Your Design x
2.4.1. Pin Assignments 2.4.2. Adding the Transceiver PLL 2.4.3. Adding the Intel® Stratix® 10 Transceiver PHY Reset Controller
4. Functional Description x
4.1. Clocking and Reset Sequence 4.2. Timing Constraints 4.3. Switching Operation Speed
5. Configuration Registers x
5.1. Register Map 5.2. Register Definitions
6. Interface Signals x
6.1. Clock and Reset Signals 6.2. Transceiver Mode and Operating Speed Signals 6.3. Serial Interface Signals 6.4. GMII Signals 6.5. XGMII Signals 6.6. Avalon® -MM Interface Signals 6.7. Transceiver Status and Reconfiguration Signals 6.8. Status Signals
1. About the 1G/2.5G/5G/10G Multi-rate Ethernet PHY Intel® FPGA IP Core
2. Getting Started
3. Parameter Settings
4. Functional Description
5. Configuration Registers
6. Interface Signals
7. 1G/2.5G/5G/10G Multi-rate Ethernet PHY Intel® Stratix® 10 FPGA IP User Guide Archives
A. Document Revision History for the 1G/2.5G/5G/10G Multi-rate Ethernet PHY Intel® Stratix® 10 FPGA IP User Guide

4.1. Clocking and Reset Sequence

Clocking Requirements:
  • For 64-bit XGMII, the 156.25 MHz clock must have zero ppm difference with reference clock of 10G transceiver PLL. Therefore, the 156.25 MHz clock must derived from the transceiver 10G reference clock for 1G/2.5G/10G (MGBASE-T) variant.
  • For 32-bit XGMII, the 312.5 MHz clock must have zero ppm difference with reference clock of 10G transceiver PLL. Therefore, the 312.5 MHz clock must derived from the transceiver 10G reference clock for 10M/100M/1G/2.5G/5G/10G (USXGMII) variant.

Reset sequence for all configurations is handled by the transceiver reset controller. For 1G/2.5G and 1G/2.5G/10G (MGBASE-T), transceiver reset sequence is automatically triggered after completion of speed switching/reconfiguration in the MAC+PHY example design.

The 1G/2.5G/5G/10G Multi-rate Ethernet PHY Intel® FPGA IP core for Intel® Stratix® 10 devices supports up to ±100 ppm clock frequency difference for a maximum packet length of 16,000 bytes.

Related Information
Level Two Title