1G/2.5G/5G/10G Multi-rate Ethernet PHY Intel® Stratix® 10 FPGA IP User Guide

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ID 683876
Date 11/15/2021
Public
Document Table of Contents
Document Table of Contents x
1. About the 1G/2.5G/5G/10G Multi-rate Ethernet PHY Intel® FPGA IP Core 2. Getting Started 3. Parameter Settings 4. Functional Description 5. Configuration Registers 6. Interface Signals 7. 1G/2.5G/5G/10G Multi-rate Ethernet PHY Intel® Stratix® 10 FPGA IP User Guide Archives A. Document Revision History for the 1G/2.5G/5G/10G Multi-rate Ethernet PHY Intel® Stratix® 10 FPGA IP User Guide
1. About the 1G/2.5G/5G/10G Multi-rate Ethernet PHY Intel® FPGA IP Core x
1.1. Features 1.2. Device Family Support 1.3. Device Speed Grade Support 1.4. Resource Utilization 1.5. Release Information
2. Getting Started x
2.1. Installing and Licensing Intel® FPGA IP Cores 2.2. Specifying the IP Core Parameters and Options 2.3. Generated File Structure 2.4. Integrating Your IP Core in Your Design
2.1. Installing and Licensing Intel® FPGA IP Cores x
2.1.1. Intel® FPGA IP Evaluation Mode
2.4. Integrating Your IP Core in Your Design x
2.4.1. Pin Assignments 2.4.2. Adding the Transceiver PLL 2.4.3. Adding the Intel® Stratix® 10 Transceiver PHY Reset Controller
4. Functional Description x
4.1. Clocking and Reset Sequence 4.2. Timing Constraints 4.3. Switching Operation Speed
5. Configuration Registers x
5.1. Register Map 5.2. Register Definitions
6. Interface Signals x
6.1. Clock and Reset Signals 6.2. Transceiver Mode and Operating Speed Signals 6.3. Serial Interface Signals 6.4. GMII Signals 6.5. XGMII Signals 6.6. Avalon® -MM Interface Signals 6.7. Transceiver Status and Reconfiguration Signals 6.8. Status Signals
1. About the 1G/2.5G/5G/10G Multi-rate Ethernet PHY Intel® FPGA IP Core
2. Getting Started
3. Parameter Settings
4. Functional Description
5. Configuration Registers
6. Interface Signals
7. 1G/2.5G/5G/10G Multi-rate Ethernet PHY Intel® Stratix® 10 FPGA IP User Guide Archives
A. Document Revision History for the 1G/2.5G/5G/10G Multi-rate Ethernet PHY Intel® Stratix® 10 FPGA IP User Guide

3. Parameter Settings

You can select the 1G/2.5G/5G/10G Multi-rate Ethernet PHY Intel® FPGA IP core for Intel® Stratix® 10 devices from the Intel® Quartus® Prime Pro Edition IP catalog. To customize the PHY IP core, specify the parameters in the IP parameter editor. The parameter editor dynamically enables the parameter options that apply to the selected operating speed.
Figure 4.  1G/2.5G/5G/10G Multi-rate Ethernet PHY IP Parameter Editor
Table 10.   1G/2.5G/5G/10G Multi-rate Ethernet PHY Intel® FPGA IP Core Parameters
Parameter Options Description
External PHY
Connect to MGBASE-T PHY On, Off Select this option when the external PHY is MGBASE-T compatible.

This parameter is enabled for 2.5G, 1G/2.5G, and 1G/2.5G/10G (MGBASE-T) modes.

Connect to NBASE-T PHY On, Off

Select this option when the external PHY is NBASE-T compatible.

This parameter is enabled for 10M/100M/1G/2.5G/5G/10G (USXGMII) modes.

PHY Options
Speed

2.5G

1G/2.5G

1G/2.5G/10G

10M/100M/1G/2.5G/5G/10G

 The operating speed of the PHY.
Enable SGMII bridge On, Off Select this parameter to enable SGMII 10-Mbps/100-Mbps/1-Gbps.

You can enable this parameter for 1G/2.5G, and 1G/2.5G/10G (MGBASE-T) modes.

Enable IEEE 1588 Precision Time Protocol On, Off Select this parameter for the PHY to provide latency information to the MAC. The MAC requires this information if it enables the IEEE 1588v2 feature.

You can enable this parameter for 2.5G, 1G/2.5G, 1G/2.5G/10G (MGBASE-T), and 10M/100M/1G/2.5G/5G/10G (USXGMII) modes provided that the SGMII bridge is disabled in 1G/2.5G and 1G/2.5G/10G (MGBASE-T) modes.

PCS Options
PHY ID (32 bit) 32-bit value

An optional 32-bit unique identifier:

  • Bits 3 to 24 of the Organizationally Unique Identifier (OUI) assigned by the IEEE
  • 6-bit model number
  • 4-bit revision number

The default value is 0x00000000.

Transceiver Options
VCCR_GXB and VCCT_GXB supply voltage for the transceivers 1.0 V, 1.1 V This parameter specifies the VCCR_GXB and VCCT_GXB transceiver supply voltage. The default setting is 1.0 V.

Use 1.1 V setting if the bank contains transceivers running at 15 Gbps or faster.

Reference clock frequency for 10 GbE (MHz) 322.265625, 644.53125 Specify the frequency of the reference clock for 10GbE.

This option is only available for 1G/2.5G/10G and 10M/100M/1G/2.5G/5G/10G (USXGMII) speed modes.

Selected TX PMA local clock division factor for 1 GbE 1, 2, 4, 8 Select the TX local clock division factor for transceiver. The selection is used for 1G Ethernet.
Selected TX PMA local clock division factor for 2.5 GbE 1, 2 Select the TX local clock division factor for transceiver. The selection is used for 2.5G Ethernet.
Dynamic Reconfiguration
Enable Native PHY Debug Master Endpoint (NPDME) On, Off When enabled, the Native PHY includes an embedded Native PHY Debug Master Endpoint (NPDME) that connects internally Avalon® -MM slave interface. The NPDME can access the reconfiguration space of the transceiver. It can perform certain test and debug functions via JTAG using the System Console.
Enable capability registers On, Off Enables capability registers. These registers provide high-level information about the transceiver channel/PLL configuration.
Set user-defined IP identifier User-specified Sets a user-defined numeric identifier that can be read from the user_identifier offset when the capability registers are enabled.
Enable control and status registers On, Off Enables soft registers for reading status signals and writing control signals on the PHY /PLL interface through the NPDME or reconfiguration interface.
Enable PRBS soft accumulators On, Off Enables soft logic to perform PRBS bit and error accumulation when using the hard PRBS generator and checker.
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