F-tile Architecture and PMA and FEC Direct PHY IP User Guide

ID 683872
Date 6/24/2022
Public

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Document Table of Contents

3.4.1. TX and RX Parallel and Serial Interface Signals

Table 38.  TX and RX Parallel and Serial Interface SignalsRefer to Variables Defining Bits for the Interfacing Ports in Port and Signal Reference for variable definitions.
Signal Name Clocks Domain/Resets Direction Description
tx_parallel_data [(80 * N * X)-1:0]

tx_coreclkin

tx_reset

input Parallel data bus from FPGA core to F-tile interface. Some bits map to specific functionality, as Parallel Data Mapping Information describes.
rx_parallel_data[(80 * N * X) -1:0]

rx_coreclkin

rx_reset

output Parallel data bus from FPGA core to F-tile interface. Some bits map to specific functionality, as TX and RX Parallel Data Mapping Information for Different Configurations describes.
tx_serial_data [N-1:0] tx_reset output TX serial data port.
tx_serial_data_n [N-1:0] tx_reset output Differential pair for TX serial data port.
rx_serial_data [N-1:0] rx_reset input RX serial data port.
rx_serial_data_n [N-1:0] rx_reset input Differential pair for RX serial data port.