F-tile Architecture and PMA and FEC Direct PHY IP User Guide

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Date 6/24/2022
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Document Table of Contents
Document Table of Contents x
1. F-tile Overview 2. F-tile Architecture 3. Implementing the F-Tile PMA/FEC Direct PHY Intel® FPGA IP 4. Implementing the F-Tile Reference and System PLL Clocks Intel® FPGA IP 5. Implementing the F-Tile Global Avalon® Memory-Mapped Interface Intel® FPGA IP 6. F-tile PMA/FEC Direct PHY Design Implementation 7. Supported Tools 8. Debugging F-Tile Transceiver Links 9. F-tile Architecture and PMA and FEC Direct PHY IP User Guide Archives 10. Document Revision History for F-tile Architecture and PMA and FEC Direct PHY IP User Guide
2. F-tile Architecture x
2.1. F-Tile Building Blocks 2.2. F-Tile Placement Rules 2.3. PMA Architecture 2.4. Clock Architecture
2.1. F-Tile Building Blocks x
2.1.1. FHT and FGT PMAs 2.1.2. 400G Hard IP and 200G Hard IP 2.1.3. PMA Data Rates 2.1.4. FEC Architecture 2.1.5. PCIe* Hard IP 2.1.6. Bonding Architecture 2.1.7. Deskew Logic 2.1.8. Embedded Multi-die Interconnect Bridge (EMIB) 2.1.9. IEEE 1588 Precision Time Protocol for Ethernet 2.1.10. Clock Networks 2.1.11. Reconfiguration Interfaces
2.2. F-Tile Placement Rules x
2.2.1. PMA-to-Fracture Mapping 2.2.2. Determining Which PMA to Map to Which Fracture 2.2.3. Hard IP Placement Rules 2.2.4. IEEE 1588 Precision Time Protocol Placement Rules 2.2.5. Topologies 2.2.6. FEC Placement Rules 2.2.7. Clock Rules and Restrictions 2.2.8. Bonding Placement Rules 2.2.9. Preserving Unused PMA Lanes
2.2.1. PMA-to-Fracture Mapping x
2.2.1.1. FHT-PMA-to-400G-Hard-IP-Fracture Mapping 2.2.1.2. FGT-PMA-to-400G-Hard-IP-Fracture Mapping 2.2.1.3. FGT-PMA-to-200G-Hard-IP-Fracture Mapping
2.2.2. Determining Which PMA to Map to Which Fracture x
2.2.2.1. Implementing One 200GbE-4 Interface with 400G Hard IP and FHT 2.2.2.2. Implementing One 200GbE-2 Interface with 400G Hard IP and FHT 2.2.2.3. Implementing One 100GbE-1 Interface with 400G Hard IP and FHT 2.2.2.4. Implementing One 100GbE-4 Interface with 400G Hard IP and FGT 2.2.2.5. Implementing One 10GbE-1 Interface with 200G Hard IP and FGT 2.2.2.6. Implementing Three 25GbE-1 Interfaces with 400G Hard IP and FHT 2.2.2.7. Implementing One 50GbE-1 and Two 25GbE-1 Interfaces with 400G Hard IP and FHT 2.2.2.8. Implementing One 100GbE-1 and Two 25GbE-1 Interfaces with 400G Hard IP and FHT 2.2.2.9. Implementing Two 100GbE-1 and One 25GbE-1 Interfaces with 400G Hard IP and FHT 2.2.2.10. Implementing 100GbE-1, 100GbE-2, and 50GbE-1 Interfaces with 400G Hard IP and FHT
2.2.5. Topologies x
2.2.5.1. Topology 5: 400G Hard IP (FHT) + 200G Hard IP (FGT) Example 2.2.5.2. Topology 14: 1x PCIe x4 + 400G Hard IP (FGT) with PTP Example
2.2.8. Bonding Placement Rules x
2.2.8.1. Bonded Lanes Use Case 1 2.2.8.2. Bonded Lanes Use Case 2
2.3. PMA Architecture x
2.3.1. FHT PMA Architecture 2.3.2. FGT PMA Architecture
2.3.1. FHT PMA Architecture x
2.3.1.1. FHT Transmitter PMA Architecture 2.3.1.2. FHT Receiver PMA Architecture 2.3.1.3. FHT PMA Loopback Modes
2.3.1.1. FHT Transmitter PMA Architecture x
2.3.1.1.1. FHT Transmitter Buffer and Phase Generator 2.3.1.1.2. FHT Serializer 2.3.1.1.3. FHT Gray-Coder and Pre-Coder 2.3.1.1.4. FHT Data Pattern Generator and Verifier
2.3.1.2. FHT Receiver PMA Architecture x
2.3.1.2.1. FHT Receiver Buffer and Equalizer 2.3.1.2.2. CDR Block 2.3.1.2.3. FHT Deserializer
2.3.2. FGT PMA Architecture x
2.3.2.1. FGT Transmitter PMA Architecture 2.3.2.2. FGT Receiver PMA Architecture 2.3.2.3. FGT PMA Tuning 2.3.2.4. FGT PMA Loopback Modes
2.3.2.1. FGT Transmitter PMA Architecture x
2.3.2.1.1. FGT Transmitter Buffer and Phase Generator 2.3.2.1.2. FGT Serializer 2.3.2.1.3. FGT Gray-Coder and Pre-Coder 2.3.2.1.4. FGT Data Pattern Generator and Verifier
2.3.2.2. FGT Receiver PMA Architecture x
2.3.2.2.1. FGT Receiver Buffer and Equalizer 2.3.2.2.2. Control Unit 2.3.2.2.3. FGT Deserializer
2.4. Clock Architecture x
2.4.1. Reference Clock Network 2.4.2. Datapath Clock Network 2.4.3. System PLL 2.4.4. Datapath Clock Cadences
2.4.1. Reference Clock Network x
2.4.1.1. FHT Reference Clock Network 2.4.1.2. FGT and System PLL Reference Clock Network 2.4.1.3. FGT Primary PLL Configuration
3. Implementing the F-Tile PMA/FEC Direct PHY Intel® FPGA IP x
3.1. F-Tile PMA/FEC Direct PHY Intel® FPGA IP Overview 3.2. Designing with F-Tile PMA/FEC Direct PHY Intel® FPGA IP 3.3. Configuring the IP 3.4. Signal and Port Reference 3.5. Bit Mapping for PMA and FEC Mode PHY TX and RX Datapath 3.6. Clocking 3.7. Custom Cadence Generation Ports and Logic 3.8. Asserting Reset 3.9. Bonding Implementation 3.10. Independent Port Configurations 3.11. Configuration Registers 3.12. Configurable Intel® Quartus® Prime Software Settings 3.13. Configuring the F-Tile PMA/FEC Direct PHY Intel® FPGA IP for Hardware Testing 3.14. Hardware Configuration Using the Avalon® Memory-Mapped Interface
3.1. F-Tile PMA/FEC Direct PHY Intel® FPGA IP Overview x
3.1.1. PMA Direct Supported Modes 3.1.2. FEC Direct Supported Modes 3.1.3. Unsupported PMA/FEC Modes
3.2. Designing with F-Tile PMA/FEC Direct PHY Intel® FPGA IP x
3.2.1. Preset IP Parameter Settings
3.3. Configuring the IP x
3.3.1. General and Common Datapath Options 3.3.2. TX Datapath Options 3.3.3. RX Datapath Options 3.3.4. RS-FEC (Reed Solomon Forward Error Correction) Options 3.3.5. Avalon® Memory Mapped Interface Options 3.3.6. Register Map IP-XACT Support 3.3.7. Example Design Generation
3.3.2. TX Datapath Options x
3.3.2.1. TX PMA interface Parameters
3.3.3. RX Datapath Options x
3.3.3.1. RX FGT PMA Interface Options
3.4. Signal and Port Reference x
3.4.1. TX and RX Parallel and Serial Interface Signals 3.4.2. TX and RX Reference Clock and Clock Output Interface Signals 3.4.3. Reset Signals 3.4.4. RS-FEC Signals 3.4.5. Custom Cadence Control and Status Signals 3.4.6. TX PMA Status Signals 3.4.7. RX PMA Status Signals 3.4.8. TX and RX PMA and Core Interface FIFO Signals 3.4.9. PMA Avalon® Memory Mapped Interface Signals 3.4.10. Datapath Avalon® Memory Mapped Interface Signals
3.4.10. Datapath Avalon® Memory Mapped Interface Signals x
3.4.10.1. Number of Datapath Memory Mapped Avalon® Interfaces and Additional Address Bits per Interface
3.5. Bit Mapping for PMA and FEC Mode PHY TX and RX Datapath x
3.5.1. Parallel Data Mapping Information 3.5.2. TX and RX Parallel Data Mapping Information for Different Configurations 3.5.3. Example of TX Parallel Data for PMA Width = 8, 10, 16, 20, 32 (X=1) 3.5.4. Example of TX Parallel Data for PMA width = 64 (X=2) 3.5.5. Example of TX Parallel Data for PMA width = 64 (X=2) for FEC Direct Mode
3.6. Clocking x
3.6.1. Clock Ports 3.6.2. Recommended tx/rx_coreclkin Connection and tx/rx_clkout2 Source 3.6.3. Port Widths and Recommended Connections for tx/rx_coreclkin, tx/rx_clkout, and tx/rx_clkout2 3.6.4. FGT PMA Fractional Mode Tuning the Fractional Value in Fractional Mode 3.6.5. FGT Core PLL Mode
3.7. Custom Cadence Generation Ports and Logic x
3.7.1. Enabling the tx_cadence_slow_clk_locked Port 3.7.2. Rate Match FIFO
3.8. Asserting Reset x
3.8.1. Reset Signal Requirements 3.8.2. Power On Reset Requirements 3.8.3. Reset Signals—Block Level 3.8.4. Reset Signals—Descriptions 3.8.5. Status Signals—Descriptions 3.8.6. Run-time Reset Sequence—TX 3.8.7. Run-time Reset Sequence—RX 3.8.8. Run-time Reset Sequence—TX + RX 3.8.9. Run-time Reset Sequence—TX with FEC
3.8.8. Run-time Reset Sequence—TX + RX x
3.8.8.1. Run-time Reset Sequence Approximate Time Durations
3.11. Configuration Registers x
3.11.1. PMA and FEC Direct PHY Soft CSR Register Map 3.11.2. FHT PMA Register Map 3.11.3. FGT PMA Register Map 3.11.4. FEC Register Map 3.11.5. Lane Offset Address 3.11.6. Logical Avalon® Memory-Mapped Port Indexing
3.11.6. Logical Avalon® Memory-Mapped Port Indexing x
3.11.6.1. FGT PMA Lane Addressing Example 1 3.11.6.2. FGT PMA Lane Addressing Example 2
3.13. Configuring the F-Tile PMA/FEC Direct PHY Intel® FPGA IP for Hardware Testing x
3.13.1. Using Debug Endpoint Interface within the F-Tile PMA/FEC Direct PHY Intel® FPGA IP 3.13.2. Using JTAG to Avalon® Master Bridge Intel FPGA IP
3.13.1. Using Debug Endpoint Interface within the F-Tile PMA/FEC Direct PHY Intel® FPGA IP x
3.13.1.1. RTL Connection Example for Debug Endpoint Avalon® Interface
3.13.2. Using JTAG to Avalon® Master Bridge Intel FPGA IP x
3.13.2.1. RTL Connection Example for JTAG to Avalon® Master Bridge Intel IP
3.14. Hardware Configuration Using the Avalon® Memory-Mapped Interface x
3.14.1. FHT PMA 3.14.2. FGT PMA
3.14.1. FHT PMA x
3.14.1.1. Enabling Loopback 3.14.1.2. Enabling the PRBS Generator and Verifier 3.14.1.3. TX Equalizer Settings 3.14.1.4. TX Error Injection 3.14.1.5. RX Reconvergence 3.14.1.6. Preserving Unused Lanes
3.14.2. FGT PMA x
3.14.2.1. Direct Register Method 3.14.2.2. FGT Attribute Access Method
3.14.2.1. Direct Register Method x
3.14.2.1.1. Direct Register Method Example
3.14.2.2. FGT Attribute Access Method x
3.14.2.2.1. FGT Attribute Access Method Example 1 3.14.2.2.2. FGT Attribute Access Method Example 2 3.14.2.2.3. FGT Attribute Access Method Example 3
4. Implementing the F-Tile Reference and System PLL Clocks Intel® FPGA IP x
4.1. IP Parameters 4.2. IP Port List 4.3. Mode of System PLL - System PLL Reference Clock and Output Frequencies 4.4. Guidelines for F-Tile Reference and System PLL Clocks Intel® FPGA IP Usage 4.5. Guidelines to Indicate all System PLL Reference Clocks are Ready
4.5. Guidelines to Indicate all System PLL Reference Clocks are Ready x
4.5.1. Example of Reference Clock Availability at Device Programming 4.5.2. Example Flow to Indicate All System PLL Reference Clocks are Ready
5. Implementing the F-Tile Global Avalon® Memory-Mapped Interface Intel® FPGA IP x
5.1. IP Parameters 5.2. IP Port List 5.3. Hardware Flow Using the F-Tile Global Avalon® Memory-Mapped Interface Intel® FPGA IP
6. F-tile PMA/FEC Direct PHY Design Implementation x
6.1. Implementing the F-tile PMA/FEC Direct PHY Design 6.2. Instantiating the F-Tile PMA/FEC Direct PHY Intel® FPGA IP 6.3. Implementing a RS-FEC Direct Design in the F-Tile PMA/FEC Direct PHY Intel® FPGA IP 6.4. Instantiating the F-Tile Reference and System PLL Clocks Intel® FPGA IP 6.5. Enabling Custom Cadence Generation Ports and Logic 6.6. Connecting the F-tile PMA/FEC Direct PHY Design IP 6.7. Simulating the F-Tile PMA/FEC Direct PHY Design 6.8. F-tile Interface Planning
6.2. Instantiating the F-Tile PMA/FEC Direct PHY Intel® FPGA IP x
6.2.1. Setting General and Common Datapath Options 6.2.2. Setting TX Datapath Options 6.2.3. Setting RX Datapath Options
6.7. Simulating the F-Tile PMA/FEC Direct PHY Design x
6.7.1. PAM4 Encoding Schemes in Simulation
6.8. F-tile Interface Planning x
6.8.1. F-tile Interface Planner Usage Example
7. Supported Tools x
7.1. F-Tile Channel Placement Tool 7.2. F-Tile PMA and FEC Direct Port Mapping Calculator 7.3. F-Tile Clocking and Datapath Tool 7.4. F-Tile TX Equalizer Tool
8. Debugging F-Tile Transceiver Links x
8.1. F-Tile Transceiver Toolkit GUI 8.2. F-Tile Transceiver Debugging Flow Walkthrough 8.3. Transceiver Toolkit Parameter Settings 8.4. Troubleshooting Common Errors
8.1. F-Tile Transceiver Toolkit GUI x
8.1.1. Collection View
8.2. F-Tile Transceiver Debugging Flow Walkthrough x
8.2.1. Modifying the Design to Enable F-Tile Transceiver Debug 8.2.2. Programming the Design into an Intel FPGA 8.2.3. Loading the Design to the Transceiver Toolkit 8.2.4. Creating Transceiver Links 8.2.5. Running BER Tests 8.2.6. Running Eye Viewer Tests 8.2.7. Running Link Optimization Tests
1. F-tile Overview
2. F-tile Architecture
3. Implementing the F-Tile PMA/FEC Direct PHY Intel® FPGA IP
4. Implementing the F-Tile Reference and System PLL Clocks Intel® FPGA IP
5. Implementing the F-Tile Global Avalon® Memory-Mapped Interface Intel® FPGA IP
6. F-tile PMA/FEC Direct PHY Design Implementation
7. Supported Tools
8. Debugging F-Tile Transceiver Links
9. F-tile Architecture and PMA and FEC Direct PHY IP User Guide Archives
10. Document Revision History for F-tile Architecture and PMA and FEC Direct PHY IP User Guide

3.6.4. FGT PMA Fractional Mode

For a given data rate, the drop-down menu lists the supported integer mode reference clock frequencies. For a given data rate, if the required reference clock frequency is not listed in the drop-down, you can either select one of the supported integer mode reference clock frequencies or enable fractional mode.

  • When enabling fractional mode, if exact fraction is not available (K = 0.25,0.5, 0.75), use 140MHz reference clock frequency for approximate fractional mode.
  • To calculate K, divide k value displayed in the IP GUI system messages; K = k / 2^22. For example, for k = 2097152, K = 0.5.
  • For a given data rate, you must enable fractional mode if you need to dynamically configure the K value during run time. When you enable fractional mode, you must enter the TX FGT PLL fractional mode reference clock frequency.

FGT PMA supports fractional mode in following PMA modes:

Table 70.  FGT PMA Support for Fractional Mode
PMA Mode Fractional Mode Support
TX simplex TX FGT PLL supports fractional mode in TX simplex. To enable, select TX simplex option for PMA mode, and turn on the Enable TX FGT PLL fractional mode in the parameter editor. The TX PLL fractional counter values automatically calculate for the selected reference clock frequency. You can place TX Simplex fractional mode on any of 16 FGT TX PMAs.
Note: FGT PMA does not support fractional mode for RX simplex.
Duplex FGT PMA in Duplex PMA mode supports fractional mode. To enable fractional mode in duplex PMA mode, select the Duplex option for PMA mode, select up to 16 for the Number of PMA lanes, and turn on Enable TX FGT PLL fractional mode option in the parameter editor.
  • In Duplex fractional mode, the output of each TX PLL is used as the reference clock for corresponding RX CDR. Each TX PLL is configured as fractional mode.
  • A separate reference clock is not required for RX CDR. TX PLL fractional counter values, and RX CDR reference clock frequency, automatically calculate for the selected reference clock frequency.
  • You can place duplex fractional mode on any of 16 FGT PMAs.
Primary PLL configuration To enable fractional mode with the primary PLL configuration, select the Duplex option for PMA mode, select 2 or 4 for the Number of PMA lanes, and turn on Enable TX FGT PLL fractional mode and Enable TX FGT PLL cascade mode options in the parameter editor.
  • In Primary PLL configuration, the TX PLL of one lane is in fractional mode and acts as the reference clock source for the local CDR and TX PLL and RX CDR blocks of other lanes (configured in integer mode) within the quad.
  • Primary PLL configuration is not supported when you select 6 ,8, 12, or 16 for the number of PMA lanes.
  • You can place the primary PLL configuration with 2 PMA lanes either on FGT PMA Lane 1 and 0 (same quad) of any quad, with Lane 1 as the primary. On FGT PMA Lane 3 and 2 (same quad) of any quad with lane 3 being the primary.
  • You can place the primary PLL configuration with 4 PMA lanes on FGT PMA Lane 3,2,1 and 0 (same quad) of any quad with Lane 3 being the primary.
  • When you place any primary PLL configuration in Quad 2, you cannot configure reference clock [8] (accessible by Quad2) as output to provide RX recovered clock.
  • When you place any primary PLL configuration in Quad 3, you cannot configure reference clock [9] (accessible by Quad3) as output to provide RX recovered clock.
Note: Refer to FGT PLL Configuration in F-tile Architecture User Guide for more information.

Tuning the Fractional Value in Fractional Mode

You can configure the F-tile FGT PMA to:
  • Transmit serial data.
  • Generate a clock for FPGA core fabric.

You can configure the FGT PMA in fractional mode to adjust the frequency and datarate by a small amount (+/- 1000ppm) for rate matching purposes. Details about how to configure the F-Tile PMA/FEC Direct PHY Intel® FPGA IP for best performance is planned to be included in future user guide releases.

Each FGT PMA has an Avalon® memory-mapped interface register containing the K value. The K value / 2^22 gives the fractional value of the feedback counter. The fractional value plus the M counter value provides the total feedback counter and determines how much PPM each bit in the K value represents.

The procedure to change the K value is:

  1. Change the K value to the new value.
  2. Pulse the strobe bit 0 -> 1-> 0 to lock in the new K value.

Each FGT PMA contains 3 PLLs; slow, medium and fast. FGT PMAs are organized in a quad. The K value and strobe bit Avalon® memory-mapped interface register addresses depend on the location of the transceiver in the quad and which PLL is used (slow, medium, fast) as shown in the table below.

Table 71.  FGT PMA Fractional K Value and Strobe Register Addresses
Channel Location in Quad PLL Fractional K Value Register Strobe Register
0 Slow 0x44000[30:9] 0x4400C[17]
Medium 0x44100[30:9] 0x4410C[17]
Fast 0x44200[30:9] 0x4420C[17]
1 Slow 0x4C000[30:9] 0x4C00C[17]
Medium 0x4C100[30:9] 0x4C10C[17]
Fast 0x4C200[30:9] 0x4C20C[17]
2 Slow 0x54000[30:9] 0x5r00C[17]
Medium 0x54100[30:9] 0x5410C[17]
Fast 0x54200[30:9] 0x5420C[17]
3 Slow 0x5C000[30:9] 0x5C00C[17]
Medium 0x5C100[30:9] 0x5C10C[17]
Fast 0x5C200[30:9] 0x5C20C[17]
You can find the transceiver location and PLL selected in the <design_name>.syn.rpt generated by the Intel® Quartus® Prime Pro Edition software as shown in the following figure.
Figure 77. Sample Intel® Quartus® Prime Pro Edition Software Synthesis Compilation Result 
; z1577a_u_ux_quad_3__ux3_synth_lc_med_en         ; enable                                   ; String        ;
; z1577a_u_ux_quad_3__ux3_synth_lc_med_f_out_hz           ; 0000000001010110011011010011111010000000 ; Unsigned Binary;
; z1577a_u_ux_quad_3__ux3_synth_lc_med_f_pfd_hz           ; 0000000000000000000000000000000000000000 ; Unsigned Binary;
; z1577a_u_ux_quad_3__ux3_synth_lc_med_f_ref_hz           ; 0000000000001000110110011110111000100000 ; Unsigned Binary;
; z1577a_u_ux_quad_3__ux3_synth_lc_med_f_rx_postdiv_hz    ; 0000000000010001010010010000110010000000 ; Unsigned Binary;
; z1577a_u_ux_quad_3__ux3_synth_lc_med_f_tx_postdiv_hz    ; 0000000000000110111010100000010100000000 ; Unsigned Binary;
; z1577a_u_ux_quad_3__ux3_synth_lc_med_f_vco_hz           ; 0000001010110011011010011111010000000000 ; Unsigned Binary;
; z1577a_u_ux_quad_3__ux3_synth_lc_med_fractional_en      ; enable                                   ; String         ;
; z1577a_u_ux_quad_3__ux3_synth_lc_med_k_counter          ; 0000111010100111001110                   ; Unsigned Binary;
; z1577a_u_ux_quad_3__ux3_synth_lc_med_l_counter          ; 001000                                   ; Unsigned Binary;
; z1577a_u_ux_quad_3__ux3_synth_lc_med_m_counter          ; 000100111                                ; Unsigned Binary;
; z1577a_u_ux_quad_3__ux3_synth_lc_med_n_counter          ; 000001                                   ; Unsigned Binary;
; z1577a_u_ux_quad_3__ux3_synth_lc_med_powerdown_mode     ; false                                    ; String         ;
; z1577a_u_ux_quad_3__ux3_synth_lc_med_primary_use        ; ux3_synth_lc_med_primary_use_disabled    ; String         ;
; z1577a_u_ux_quad_3__ux3_synth_lc_med_rx_postdiv_counter ; 00101000                                 ; Unsigned Binary;
; z1577a_u_ux_quad_3__ux3_synth_lc_med_tx_postdiv_counter ; 01100100                                 ; Unsigned Binary;
; z1577a_u_ux_quad_3__ux3_synth_lc_med_tx_postdiv_fractional_en ; disable                            ; String         ;
In the sample compilation result shown above, the FGT PMA is placed in quad 3, channel 3 and the medium PLL is used. The M counter is 39 (000100111) and the nominal K value is 0.057 (0000111010100111001110/2^22). Each LSB in the K value represents 6 ppb (parts per billion) (1/2^22/39.057). The K value register address is 0x5C100[30:9] and the strobe register bit address is 0x5C10C[17].
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