F-tile Architecture and PMA and FEC Direct PHY IP User Guide

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Date 6/24/2022
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Document Table of Contents
Document Table of Contents x
1. F-tile Overview 2. F-tile Architecture 3. Implementing the F-Tile PMA/FEC Direct PHY Intel® FPGA IP 4. Implementing the F-Tile Reference and System PLL Clocks Intel® FPGA IP 5. Implementing the F-Tile Global Avalon® Memory-Mapped Interface Intel® FPGA IP 6. F-tile PMA/FEC Direct PHY Design Implementation 7. Supported Tools 8. Debugging F-Tile Transceiver Links 9. F-tile Architecture and PMA and FEC Direct PHY IP User Guide Archives 10. Document Revision History for F-tile Architecture and PMA and FEC Direct PHY IP User Guide
2. F-tile Architecture x
2.1. F-Tile Building Blocks 2.2. F-Tile Placement Rules 2.3. PMA Architecture 2.4. Clock Architecture
2.1. F-Tile Building Blocks x
2.1.1. FHT and FGT PMAs 2.1.2. 400G Hard IP and 200G Hard IP 2.1.3. PMA Data Rates 2.1.4. FEC Architecture 2.1.5. PCIe* Hard IP 2.1.6. Bonding Architecture 2.1.7. Deskew Logic 2.1.8. Embedded Multi-die Interconnect Bridge (EMIB) 2.1.9. IEEE 1588 Precision Time Protocol for Ethernet 2.1.10. Clock Networks 2.1.11. Reconfiguration Interfaces
2.2. F-Tile Placement Rules x
2.2.1. PMA-to-Fracture Mapping 2.2.2. Determining Which PMA to Map to Which Fracture 2.2.3. Hard IP Placement Rules 2.2.4. IEEE 1588 Precision Time Protocol Placement Rules 2.2.5. Topologies 2.2.6. FEC Placement Rules 2.2.7. Clock Rules and Restrictions 2.2.8. Bonding Placement Rules 2.2.9. Preserving Unused PMA Lanes
2.2.1. PMA-to-Fracture Mapping x
2.2.1.1. FHT-PMA-to-400G-Hard-IP-Fracture Mapping 2.2.1.2. FGT-PMA-to-400G-Hard-IP-Fracture Mapping 2.2.1.3. FGT-PMA-to-200G-Hard-IP-Fracture Mapping
2.2.2. Determining Which PMA to Map to Which Fracture x
2.2.2.1. Implementing One 200GbE-4 Interface with 400G Hard IP and FHT 2.2.2.2. Implementing One 200GbE-2 Interface with 400G Hard IP and FHT 2.2.2.3. Implementing One 100GbE-1 Interface with 400G Hard IP and FHT 2.2.2.4. Implementing One 100GbE-4 Interface with 400G Hard IP and FGT 2.2.2.5. Implementing One 10GbE-1 Interface with 200G Hard IP and FGT 2.2.2.6. Implementing Three 25GbE-1 Interfaces with 400G Hard IP and FHT 2.2.2.7. Implementing One 50GbE-1 and Two 25GbE-1 Interfaces with 400G Hard IP and FHT 2.2.2.8. Implementing One 100GbE-1 and Two 25GbE-1 Interfaces with 400G Hard IP and FHT 2.2.2.9. Implementing Two 100GbE-1 and One 25GbE-1 Interfaces with 400G Hard IP and FHT 2.2.2.10. Implementing 100GbE-1, 100GbE-2, and 50GbE-1 Interfaces with 400G Hard IP and FHT
2.2.5. Topologies x
2.2.5.1. Topology 5: 400G Hard IP (FHT) + 200G Hard IP (FGT) Example 2.2.5.2. Topology 14: 1x PCIe x4 + 400G Hard IP (FGT) with PTP Example
2.2.8. Bonding Placement Rules x
2.2.8.1. Bonded Lanes Use Case 1 2.2.8.2. Bonded Lanes Use Case 2
2.3. PMA Architecture x
2.3.1. FHT PMA Architecture 2.3.2. FGT PMA Architecture
2.3.1. FHT PMA Architecture x
2.3.1.1. FHT Transmitter PMA Architecture 2.3.1.2. FHT Receiver PMA Architecture 2.3.1.3. FHT PMA Loopback Modes
2.3.1.1. FHT Transmitter PMA Architecture x
2.3.1.1.1. FHT Transmitter Buffer and Phase Generator 2.3.1.1.2. FHT Serializer 2.3.1.1.3. FHT Gray-Coder and Pre-Coder 2.3.1.1.4. FHT Data Pattern Generator and Verifier
2.3.1.2. FHT Receiver PMA Architecture x
2.3.1.2.1. FHT Receiver Buffer and Equalizer 2.3.1.2.2. CDR Block 2.3.1.2.3. FHT Deserializer
2.3.2. FGT PMA Architecture x
2.3.2.1. FGT Transmitter PMA Architecture 2.3.2.2. FGT Receiver PMA Architecture 2.3.2.3. FGT PMA Tuning 2.3.2.4. FGT PMA Loopback Modes
2.3.2.1. FGT Transmitter PMA Architecture x
2.3.2.1.1. FGT Transmitter Buffer and Phase Generator 2.3.2.1.2. FGT Serializer 2.3.2.1.3. FGT Gray-Coder and Pre-Coder 2.3.2.1.4. FGT Data Pattern Generator and Verifier
2.3.2.2. FGT Receiver PMA Architecture x
2.3.2.2.1. FGT Receiver Buffer and Equalizer 2.3.2.2.2. Control Unit 2.3.2.2.3. FGT Deserializer
2.4. Clock Architecture x
2.4.1. Reference Clock Network 2.4.2. Datapath Clock Network 2.4.3. System PLL 2.4.4. Datapath Clock Cadences
2.4.1. Reference Clock Network x
2.4.1.1. FHT Reference Clock Network 2.4.1.2. FGT and System PLL Reference Clock Network 2.4.1.3. FGT Primary PLL Configuration
3. Implementing the F-Tile PMA/FEC Direct PHY Intel® FPGA IP x
3.1. F-Tile PMA/FEC Direct PHY Intel® FPGA IP Overview 3.2. Designing with F-Tile PMA/FEC Direct PHY Intel® FPGA IP 3.3. Configuring the IP 3.4. Signal and Port Reference 3.5. Bit Mapping for PMA and FEC Mode PHY TX and RX Datapath 3.6. Clocking 3.7. Custom Cadence Generation Ports and Logic 3.8. Asserting Reset 3.9. Bonding Implementation 3.10. Independent Port Configurations 3.11. Configuration Registers 3.12. Configurable Intel® Quartus® Prime Software Settings 3.13. Configuring the F-Tile PMA/FEC Direct PHY Intel® FPGA IP for Hardware Testing 3.14. Hardware Configuration Using the Avalon® Memory-Mapped Interface
3.1. F-Tile PMA/FEC Direct PHY Intel® FPGA IP Overview x
3.1.1. PMA Direct Supported Modes 3.1.2. FEC Direct Supported Modes 3.1.3. Unsupported PMA/FEC Modes
3.2. Designing with F-Tile PMA/FEC Direct PHY Intel® FPGA IP x
3.2.1. Preset IP Parameter Settings
3.3. Configuring the IP x
3.3.1. General and Common Datapath Options 3.3.2. TX Datapath Options 3.3.3. RX Datapath Options 3.3.4. RS-FEC (Reed Solomon Forward Error Correction) Options 3.3.5. Avalon® Memory Mapped Interface Options 3.3.6. Register Map IP-XACT Support 3.3.7. Example Design Generation
3.3.2. TX Datapath Options x
3.3.2.1. TX PMA interface Parameters
3.3.3. RX Datapath Options x
3.3.3.1. RX FGT PMA Interface Options
3.4. Signal and Port Reference x
3.4.1. TX and RX Parallel and Serial Interface Signals 3.4.2. TX and RX Reference Clock and Clock Output Interface Signals 3.4.3. Reset Signals 3.4.4. RS-FEC Signals 3.4.5. Custom Cadence Control and Status Signals 3.4.6. TX PMA Status Signals 3.4.7. RX PMA Status Signals 3.4.8. TX and RX PMA and Core Interface FIFO Signals 3.4.9. PMA Avalon® Memory Mapped Interface Signals 3.4.10. Datapath Avalon® Memory Mapped Interface Signals
3.4.10. Datapath Avalon® Memory Mapped Interface Signals x
3.4.10.1. Number of Datapath Memory Mapped Avalon® Interfaces and Additional Address Bits per Interface
3.5. Bit Mapping for PMA and FEC Mode PHY TX and RX Datapath x
3.5.1. Parallel Data Mapping Information 3.5.2. TX and RX Parallel Data Mapping Information for Different Configurations 3.5.3. Example of TX Parallel Data for PMA Width = 8, 10, 16, 20, 32 (X=1) 3.5.4. Example of TX Parallel Data for PMA width = 64 (X=2) 3.5.5. Example of TX Parallel Data for PMA width = 64 (X=2) for FEC Direct Mode
3.6. Clocking x
3.6.1. Clock Ports 3.6.2. Recommended tx/rx_coreclkin Connection and tx/rx_clkout2 Source 3.6.3. Port Widths and Recommended Connections for tx/rx_coreclkin, tx/rx_clkout, and tx/rx_clkout2 3.6.4. FGT PMA Fractional Mode 3.6.5. FGT Core PLL Mode
3.7. Custom Cadence Generation Ports and Logic x
3.7.1. Enabling the tx_cadence_slow_clk_locked Port 3.7.2. Rate Match FIFO
3.8. Asserting Reset x
3.8.1. Reset Signal Requirements 3.8.2. Power On Reset Requirements 3.8.3. Reset Signals—Block Level 3.8.4. Reset Signals—Descriptions 3.8.5. Status Signals—Descriptions 3.8.6. Run-time Reset Sequence—TX 3.8.7. Run-time Reset Sequence—RX 3.8.8. Run-time Reset Sequence—TX + RX 3.8.9. Run-time Reset Sequence—TX with FEC
3.8.8. Run-time Reset Sequence—TX + RX x
3.8.8.1. Run-time Reset Sequence Approximate Time Durations
3.11. Configuration Registers x
3.11.1. PMA and FEC Direct PHY Soft CSR Register Map 3.11.2. FHT PMA Register Map 3.11.3. FGT PMA Register Map 3.11.4. FEC Register Map 3.11.5. Lane Offset Address 3.11.6. Logical Avalon® Memory-Mapped Port Indexing
3.11.6. Logical Avalon® Memory-Mapped Port Indexing x
3.11.6.1. FGT PMA Lane Addressing Example 1 3.11.6.2. FGT PMA Lane Addressing Example 2
3.13. Configuring the F-Tile PMA/FEC Direct PHY Intel® FPGA IP for Hardware Testing x
3.13.1. Using Debug Endpoint Interface within the F-Tile PMA/FEC Direct PHY Intel® FPGA IP 3.13.2. Using JTAG to Avalon® Master Bridge Intel FPGA IP
3.13.1. Using Debug Endpoint Interface within the F-Tile PMA/FEC Direct PHY Intel® FPGA IP x
3.13.1.1. RTL Connection Example for Debug Endpoint Avalon® Interface
3.13.2. Using JTAG to Avalon® Master Bridge Intel FPGA IP x
3.13.2.1. RTL Connection Example for JTAG to Avalon® Master Bridge Intel IP
3.14. Hardware Configuration Using the Avalon® Memory-Mapped Interface x
3.14.1. FHT PMA 3.14.2. FGT PMA
3.14.1. FHT PMA x
3.14.1.1. Enabling Loopback 3.14.1.2. Enabling the PRBS Generator and Verifier 3.14.1.3. TX Equalizer Settings 3.14.1.4. TX Error Injection 3.14.1.5. RX Reconvergence 3.14.1.6. Preserving Unused Lanes
3.14.2. FGT PMA x
3.14.2.1. Direct Register Method 3.14.2.2. FGT Attribute Access Method
3.14.2.1. Direct Register Method x
3.14.2.1.1. Direct Register Method Example
3.14.2.2. FGT Attribute Access Method x
3.14.2.2.1. FGT Attribute Access Method Example 1 3.14.2.2.2. FGT Attribute Access Method Example 2 3.14.2.2.3. FGT Attribute Access Method Example 3
4. Implementing the F-Tile Reference and System PLL Clocks Intel® FPGA IP x
4.1. IP Parameters 4.2. IP Port List 4.3. Mode of System PLL - System PLL Reference Clock and Output Frequencies 4.4. Guidelines for F-Tile Reference and System PLL Clocks Intel® FPGA IP Usage 4.5. Guidelines to Indicate all System PLL Reference Clocks are Ready
4.5. Guidelines to Indicate all System PLL Reference Clocks are Ready x
4.5.1. Example of Reference Clock Availability at Device Programming 4.5.2. Example Flow to Indicate All System PLL Reference Clocks are Ready
5. Implementing the F-Tile Global Avalon® Memory-Mapped Interface Intel® FPGA IP x
5.1. IP Parameters 5.2. IP Port List 5.3. Hardware Flow Using the F-Tile Global Avalon® Memory-Mapped Interface Intel® FPGA IP
6. F-tile PMA/FEC Direct PHY Design Implementation x
6.1. Implementing the F-tile PMA/FEC Direct PHY Design 6.2. Instantiating the F-Tile PMA/FEC Direct PHY Intel® FPGA IP 6.3. Implementing a RS-FEC Direct Design in the F-Tile PMA/FEC Direct PHY Intel® FPGA IP 6.4. Instantiating the F-Tile Reference and System PLL Clocks Intel® FPGA IP 6.5. Enabling Custom Cadence Generation Ports and Logic 6.6. Connecting the F-tile PMA/FEC Direct PHY Design IP 6.7. Simulating the F-Tile PMA/FEC Direct PHY Design 6.8. F-tile Interface Planning
6.2. Instantiating the F-Tile PMA/FEC Direct PHY Intel® FPGA IP x
6.2.1. Setting General and Common Datapath Options 6.2.2. Setting TX Datapath Options 6.2.3. Setting RX Datapath Options
6.7. Simulating the F-Tile PMA/FEC Direct PHY Design x
6.7.1. PAM4 Encoding Schemes in Simulation
6.8. F-tile Interface Planning x
6.8.1. F-tile Interface Planner Usage Example
7. Supported Tools x
7.1. F-Tile Channel Placement Tool 7.2. F-Tile PMA and FEC Direct Port Mapping Calculator 7.3. F-Tile Clocking and Datapath Tool 7.4. F-Tile TX Equalizer Tool
8. Debugging F-Tile Transceiver Links x
8.1. F-Tile Transceiver Toolkit GUI 8.2. F-Tile Transceiver Debugging Flow Walkthrough 8.3. Transceiver Toolkit Parameter Settings 8.4. Troubleshooting Common Errors
8.1. F-Tile Transceiver Toolkit GUI x
8.1.1. Collection View
8.2. F-Tile Transceiver Debugging Flow Walkthrough x
8.2.1. Modifying the Design to Enable F-Tile Transceiver Debug 8.2.2. Programming the Design into an Intel FPGA 8.2.3. Loading the Design to the Transceiver Toolkit 8.2.4. Creating Transceiver Links 8.2.5. Running BER Tests 8.2.6. Running Eye Viewer Tests 8.2.7. Running Link Optimization Tests
1. F-tile Overview
2. F-tile Architecture
3. Implementing the F-Tile PMA/FEC Direct PHY Intel® FPGA IP
4. Implementing the F-Tile Reference and System PLL Clocks Intel® FPGA IP
5. Implementing the F-Tile Global Avalon® Memory-Mapped Interface Intel® FPGA IP
6. F-tile PMA/FEC Direct PHY Design Implementation
7. Supported Tools
8. Debugging F-Tile Transceiver Links
9. F-tile Architecture and PMA and FEC Direct PHY IP User Guide Archives
10. Document Revision History for F-tile Architecture and PMA and FEC Direct PHY IP User Guide

3.11.6. Logical Avalon® Memory-Mapped Port Indexing

This section explains how to access the FGT PMA lanes if your design has more than four FGT PMA lanes that span across multiple FGT quads, or if you place the FGT PMA lane across different FGT quads. You need to know how to control the logical Avalon® memory-mapped port indexing if you are using the shared reconfiguration interface. (Enable separate Avalon interface per PMA = Off). The Logical Avalon® Memory-Mapped Port Indexing is only applicable for FGT PMA lanes and not for FHT PMA lanes.

If your design has the Enable separate Avalon interface per fracture = On feature enabled, each datapath and PMA Avalon® memory-mapped interface has its own reconfiguration interface and you can directly access the port’s register address without following the logical port indexing instruction explained in this section.

The reconfiguration address bus for one PMA lane in the F-Tile PMA/FEC Direct PHY Intel® FPGA IP is:
  • 14 bits for the datapath Avalon memory-mapped reconfiguration interface (reconfig_pdp_address[13:0])
  • 18 bits for the PMA Avalon memory-mapped reconfiguration interface (reconfig_xcvr_address[17:0])

The reconfiguration address space grows as a function of the following equation:

log2(N)

(where N = number of lanes), for an increase in the number of PMA lanes. The additional MSB bits of the reconfiguration address bus represent the logical Avalon® memory-mapped port index value. Refer to MSB Address Bits for PMA Logical Avalon® Memory-Mapped Reconfiguration Port Index Value and MSB Address Bits for Datapath Logical Avalon® Memory-Mapped Reconfiguration Port Index Value for more information.

Note: When you Enable RS-FEC mode, the reconfig_pdp_address bus width does not increase for the datapath Avalon® memory-mapped reconfiguration interface. Refer to Variables Defining Bits for the Interfacing Ports in Port and Signal Reference for more information about the Kd and Kp formula and the MSB bits for the logical Avalon® memory-mapped port indexing information.

For example, if you enable 16 PMA lanes in your design, for the PMA Avalon® memory-mapped interface, the total reconfiguration address bus is reconfig_xcvr_address[21:0]. The PMA Avalon® memory-mapped interfaces MSB address bits (reconfig_xcvr_address[21:18]) provide the logical mapping to access different lanes and quads based on the number of PMA lanes. The 4 additional MSB address bits (reconfig_xcvr_address[21:18]) are a logical representation of the PMA Avalon® memory-mapped interface port. You can use them to read or write to the individual PMA Avalon® memory-mapped interface defined within the F-Tile PMA/FEC Direct PHY Intel® FPGA IP. The following table shows the MSB address bits for PMA logical Avalon® memory-mapped port indexing with the number of PMA lanes configured in the F-Tile PMA/FEC Direct PHY Intel® FPGA IP.

Table 80.  MSB Address Bits for PMA Logical Avalon® Memory-Mapped Reconfiguration Port Index Value
PMA Lane Set in GUI(s) Reconfiguration Address Bus MSB Address Bits for PMA Logical Avalon® Memory-Mapped Port Indexing PMA Logical Avalon® Memory-Mapped Port Indexing (value=hex)
1 reconfig_xcvr_address[17:0] Not Applicable 0
2 reconfig_xcvr_address[18:0] [18] 0,1
4 reconfig_xcvr_address[19:0] [19:18] 0,1,2,3
6, 8 reconfig_xcvr_address[20:0] [20:18] 0,1,2,3,4,5,6,7
12, 16 reconfig_xcvr_address[21:0] [21:18] 0,1,2,3,4,5,6,7,8,9,A,B,C,D,E,F

Similarly, the datapath Avalon® memory-mapped interface's MSB address bits (reconfig_pdp_address[17:14]) provide the logical mapping to access different lanes and quads based on the number of PMA lanes. The datapath Avalon® memory-mapped interfaces MSB address bits (reconfig_pdp_address[17:14]) are a logical representation of the datapath Avalon® memory-mapped interface port. You can use them to read or write to the individual datapath Avalon® memory-mapped interface ports defined within the F-Tile PMA/FEC Direct PHY Intel® FPGA IP. The following table shows the MSB address bits for datapath logical Avalon® memory-mapped port indexing with the number of PMA lanes configured in the F-Tile PMA/FEC Direct PHY Intel® FPGA IP.

Table 81.  MSB Address Bits for Datapath Logical Avalon® Memory-Mapped Reconfiguration Port Index Value
PMA Lane Set in GUI(s) Reconfiguration Address Bus MSB Address Bits for Datapath Logical Avalon® Memory-Mapped Port Indexing Datapath Logical Avalon® Memory-Mapped Port Indexing (value= hex)
1 reconfig_pdp_address[13:0] Not Applicable 0
2 reconfig_pdp_address[14:0] [14] 0,1
4 reconfig_pdp_address[15:0] [15:14] 0,1,2,3
6, 8 reconfig_pdp_address[16:0] [16:14] 0,1,2,3,4,5,6,7
12, 16 reconfig_pdp_address[17:0] [17:14] 0,1,2,3,4,5,6,7,8,9,A,B,C,D,E,F
The following table shows the datapath and PMA logical Avalon® memory-mapped port index value and the offset address for FGT PMA registers. Add the additional MSB address bits [3:0] to the 20-bit register offset address [19:0] to control the different PMA lanes in your design. For example:
  • If the Avalon® memory-mapped port index value = 0x0 and the offset address is 0x48000. You write to 0x048000.
  • If the Avalon® memory-mapped port index value = 0x2 and the offset address is 0x58000. You write to 0x258000.
Table 82.  Datapath and PMA Logical Avalon® Memory-Mapped Port Index and PMA Offset Address Register Value
Quad Lane Datapath and PMA Logical Avalon® Memory-Mapped Port Index [3:0] Offset Address
0 0 0x0 0x40000
1 0x1 0x48000
2 0x2 0x50000
3 0x3 0x58000
1 0 0x4 0x40000
1 0x5 0x48000
2 0x6 0x50000
3 0x7 0x58000
2 0 0x8 0x40000
1 0x9 0x48000
2 0xA 0x50000
3 0xB 0x58000
3 0 0xC 0x40000
1 0xD 0x48000
2 0xE 0x50000
3 0xF 0x58000

Section Content
FGT PMA Lane Addressing Example 1
FGT PMA Lane Addressing Example 2

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