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Ixiasoft
1. F-tile Overview
2. F-tile Architecture
3. Implementing the F-Tile PMA/FEC Direct PHY Intel® FPGA IP
4. Implementing the F-Tile Reference and System PLL Clocks Intel® FPGA IP
5. Implementing the F-Tile Global Avalon® Memory-Mapped Interface Intel® FPGA IP
6. F-tile PMA/FEC Direct PHY Design Example Implementation
7. Supported Tools
8. Debugging F-Tile Transceiver Links
9. F-tile Architecture and PMA and FEC Direct PHY IP User Guide Archives
10. Document Revision History for F-tile Architecture and PMA and FEC Direct PHY IP User Guide
2.1.1. FHT and FGT PMAs
2.1.2. 400G Hard IP and 200G Hard IP
2.1.3. PMA Data Rates
2.1.4. FEC Architecture
2.1.5. PCIe* Hard IP
2.1.6. Bonding Architecture
2.1.7. Deskew Logic
2.1.8. Embedded Multi-die Interconnect Bridge (EMIB)
2.1.9. IEEE 1588 Precision Time Protocol for Ethernet
2.1.10. Clock Networks
2.1.11. Reconfiguration Interfaces
2.2.1. PMA-to-Fracture Mapping
2.2.2. Determining Which PMA to Map to Which Fracture
2.2.3. Hard IP Placement Rules
2.2.4. IEEE 1588 Precision Time Protocol Placement Rules
2.2.5. Topologies
2.2.6. FEC Placement Rules
2.2.7. Clock Rules and Restrictions
2.2.8. Bonding Placement Rules
2.2.9. Preserving Unused PMA Lanes
2.2.2.1. Implementing One 200GbE-4 Interface with 400G Hard IP and FHT
2.2.2.2. Implementing One 200GbE-2 Interface with 400G Hard IP and FHT
2.2.2.3. Implementing One 100GbE-1 Interface with 400G Hard IP and FHT
2.2.2.4. Implementing One 100GbE-4 Interface with 400G Hard IP and FGT
2.2.2.5. Implementing One 10GbE-1 Interface with 200G Hard IP and FGT
2.2.2.6. Implementing Three 25GbE-1 Interfaces with 400G Hard IP and FHT
2.2.2.7. Implementing One 50GbE-1 and Two 25GbE-1 Interfaces with 400G Hard IP and FHT
2.2.2.8. Implementing One 100GbE-1 and Two 25GbE-1 Interfaces with 400G Hard IP and FHT
2.2.2.9. Implementing Two 100GbE-1 and One 25GbE-1 Interfaces with 400G Hard IP and FHT
2.2.2.10. Implementing 100GbE-1, 100GbE-2, and 50GbE-1 Interfaces with 400G Hard IP and FHT
3.1. F-Tile PMA/FEC Direct PHY Intel® FPGA IP Overview
3.2. Designing with F-Tile PMA/FEC Direct PHY Intel® FPGA IP
3.3. Configuring the IP
3.4. Signal and Port Reference
3.5. Bit Mapping for PMA and FEC Mode PHY TX and RX Datapath
3.6. Clocking
3.7. Custom Cadence Generation Ports and Logic
3.8. Asserting Reset
3.9. Bonding Implementation
3.10. Independent Port Configurations
3.11. Configuration Registers
3.12. Configurable Intel® Quartus® Prime Software Settings
3.13. Configuring the F-Tile PMA/FEC Direct PHY Intel® FPGA IP for Hardware Testing
3.14. Hardware Configuration Using the Avalon® Memory-Mapped Interface
3.4.1. TX and RX Parallel and Serial Interface Signals
3.4.2. TX and RX Reference Clock and Clock Output Interface Signals
3.4.3. Reset Signals
3.4.4. RS-FEC Signals
3.4.5. Custom Cadence Control and Status Signals
3.4.6. TX PMA Status Signals
3.4.7. RX PMA Status Signals
3.4.8. TX and RX PMA and Core Interface FIFO Signals
3.4.9. PMA Avalon® Memory Mapped Interface Signals
3.4.10. Datapath Avalon® Memory Mapped Interface Signals
3.5.1. Parallel Data Mapping Information
3.5.2. TX and RX Parallel Data Mapping Information for Different Configurations
3.5.3. Example of TX Parallel Data for PMA Width = 8, 10, 16, 20, 32 (X=1)
3.5.4. Example of TX Parallel Data for PMA width = 64 (X=2)
3.5.5. Example of TX Parallel Data for PMA width = 64 (X=2) for FEC Direct Mode
3.8.1. Reset Signal Requirements
3.8.2. Power On Reset Requirements
3.8.3. Reset Signals—Block Level
3.8.4. Reset Signals—Descriptions
3.8.5. Status Signals—Descriptions
3.8.6. Run-time Reset Sequence—TX
3.8.7. Run-time Reset Sequence—RX
3.8.8. Run-time Reset Sequence—TX + RX
3.8.9. Run-time Reset Sequence—TX with FEC
6.1. Implementing the F-tile PMA/FEC Direct PHY Design Example
6.2. Instantiating the F-Tile PMA/FEC Direct PHY Intel® FPGA IP
6.3. Implementing a RS-FEC Direct Design in the F-Tile PMA/FEC Direct PHY Intel® FPGA IP
6.4. Instantiating the F-Tile Reference and System PLL Clocks Intel® FPGA IP
6.5. Enabling Custom Cadence Generation Ports and Logic
6.6. Connecting the F-tile PMA/FEC Direct PHY Design IP
6.7. Simulating the F-Tile PMA/FEC Direct PHY Design Example
6.8. F-tile Interface Planning
Visible to Intel only — GUID: odk1614284547530
Ixiasoft
4.1. IP Parameters
Parameter | Values | Description |
---|---|---|
System PLL #0 | ||
Mode of system PLL | 0, 1, 2 | Selects the mode of system PLL #0.
|
User configuration | ||
User PCIe-based configuration | ||
ETHERNET_FREQ_805_156 | ||
ETHERNET_FREQ_805_312 | ||
ETHERNET_FREQ_805_322 35. | ||
ETHERNET_FREQ_830_156 | ||
ETHERNET_FREQ_830_312 | ||
PCIE_FREQ_1000 | ||
PCIE_FREQ_500 | ||
PCIE_FREQ_550 | ||
PCIE_FREQ_600 | ||
PCIE_FREQ_650 | ||
PCIE_FREQ_700 | ||
PCIE_FREQ_750 | ||
PCIE_FREQ_800 | ||
PCIE_FREQ_850 | ||
PCIE_FREQ_900 | ||
PCIE_FREQ_950 | ||
Reference clock source | Reference clock #0 | Selects the logical reference clock source for system PLL #0. The reference clock source can be shared with FGT PMA and other system PLLs. The default value is Reference clock #0. |
Reference clock #1 | ||
Reference clock #2 | ||
Reference clock #3 | ||
Reference clock #4 | ||
Reference clock #5 | ||
Reference clock #6 | ||
Reference clock #7 | ||
Reference clock #8 | ||
Reference clock #9 | ||
Output frequency | 31.25 to 1000 MHz | Specifies the output frequency of the system PLL #0 in MHz. In background, the algorithm calculates the legal reference clock frequencies for that clock output frequency. For correct calculation, specify the exact frequency with decimal points. The default value is 805.6640625. |
System PLL #1 | ||
Mode of system PLL | 0, 1, 2 | Selects the mode of system PLL #1.
|
User configuration | ||
User PCIE-based configuration | ||
ETHERNET_FREQ_805_156 | ||
ETHERNET_FREQ_805_312 | ||
ETHERNET_FREQ_805_322 35. | ||
ETHERNET_FREQ_830_156 | ||
ETHERNET_FREQ_830_312 | ||
ETHERNET_FREQ_830_312 | ||
PCIE_FREQ_1000 | ||
PCIE_FREQ_500 | ||
PCIE_FREQ_550 | ||
PCIE_FREQ_600 | ||
PCIE_FREQ_650 | ||
PCIE_FREQ_700 | ||
PCIE_FREQ_750 | ||
PCIE_FREQ_800 | ||
PCIE_FREQ_850 | ||
PCIE_FREQ_900 | ||
PCIE_FREQ_950 | ||
Reference clock source | Reference clock #0 | Selects the logical reference clock source for system PLL #1. The reference clock source can be shared with FGT PMA and other system PLLs. |
Reference clock #1 | ||
Reference clock #2 | ||
Reference clock #3 | ||
Reference clock #4 | ||
Reference clock #5 | ||
Reference clock #6 | ||
Reference clock #7 | ||
Reference clock #8 | ||
Reference clock #9 | ||
Output frequency | 31.25 to 1000 MHz | Specifies the output frequency of the system PLL #1 in MHz. In background, the algorithm calculates the legal reference clock frequencies for that clock output frequency. For correct calculation, must specify the exact frequency with decimal points. |
System PLL #2 | ||
Mode of system PLL | 0, 1, 2 | Selects the mode of system PLL #2.
|
User configuration | ||
User PCIE-based configuration | ||
ETHERNET_FREQ_805_156 | ||
ETHERNET_FREQ_805_312 | ||
ETHERNET_FREQ_805_322 35. | ||
ETHERNET_FREQ_830_156 | ||
ETHERNET_FREQ_830_312 | ||
ETHERNET_FREQ_830_312 | ||
PCIE_FREQ_1000 | ||
PCIE_FREQ_500 | ||
PCIE_FREQ_550 | ||
PCIE_FREQ_600 | ||
PCIE_FREQ_650 | ||
PCIE_FREQ_700 | ||
PCIE_FREQ_750 | ||
PCIE_FREQ_800 | ||
PCIE_FREQ_850 | ||
PCIE_FREQ_900 | ||
PCIE_FREQ_950 | ||
Reference clock source | Reference clock #0 | Selects the logical reference clock source for system PLL #2. The reference clock source can be shared with FGT PMA and other system PLLs. |
Reference clock #1 | ||
Reference clock #2 | ||
Reference clock #3 | ||
Reference clock #4 | ||
Reference clock #5 | ||
Reference clock #6 | ||
Reference clock #7 | ||
Reference clock #8 | ||
Reference clock #9 | ||
Output Frequency | 31.25 to 1000 MHz | Specifies the output frequency of the system PLL #2 in MHz. In background, the algorithm calculates the legal reference clock frequencies for that clock output frequency. For correct calculation, must specify the exact frequency with decimal points. |
FHT Common PLL | ||
Controller source | Auto, CommonPLL A, CommonPLL B | If both common PLLs are enabled, this selection specifies the common PLL that drives the FHT microcontroller. The reference clock that drives this common PLL must be present and stable throughout F-tile operation. |
FHT Common PLL A | ||
Enable FHT Common PLL A | On/Off | Enable/Disable FHT common PLL A. When enabled, must provide FHT reference clock source and frequency. The default value is Off. |
FHT reference clock source | FHT reference clock #0 | Specifies the logical reference clock source for FHT common PLL A. The default value is FHT reference clock #0. |
FHT reference clock #1 | ||
FHT Common PLL B | ||
Enable FHT Common PLL B | On/Off | When enabled, must provide FHT reference clock source and frequency. The default value is Off. |
FHT reference clock source | FHT reference clock #0 | Specifies the logical reference clock source for FHT common PLL B. The default value is FHT Reference clock #0. |
FHT reference clock #1 | ||
Reference clock(s) | ||
FGT/System PLL | ||
Enable reference clock #0 for FGT PMA | On/Off | Enables logical reference clock #0 for FGT PMA. This reference clock can also be shared by system PLL. The default value is Off. |
Reference clock frequency #0 | 25 to 380 MHz | Specifies the reference clock #0 frequency. Range is:
|
Enable Reference clock #1 for FGT PMA | On/Off | Enables logical reference clock #1 for FGT PMA. This reference clock can also be shared by system PLL. The default value is Off. |
Reference clock frequency #1 | 25 to 380 MHz | Specifies the reference clock #1 frequency. Range is:
|
Enable Reference clock #2 for FGT PMA | On/Off | Enable logical reference clock #2 for FGT PMA. This reference clock can also be shared by system PLL. The default value is Off. |
Reference clock frequency #2 | 25 to 380 MHz | Specifies the reference clock #2 frequency. Range is:
|
Enable Reference clock #3 for FGT PMA | On/Off | Enable logical reference clock #3 for FGT PMA. This reference clock can also be shared by system PLL. The default value is Off. |
Reference clock frequency #3 | 25 to 380 MHz | Specifies the reference clock #3 frequency. Range is:
|
Enable Reference clock #4 for FGT PMA | On/Off | Enable logical reference clock #4 for FGT PMA. This reference clock can also be shared by system PLL. The default value is Off. |
Reference clock frequency #4 | 25 to 380 MHz | Specifies the reference clock #4 frequency. Range is:
|
Enable Reference clock #5 for FGT PMA | On/Off | Enable logical reference clock #5 for FGT PMA. This reference clock can also be shared by system PLL. The default value is Off. |
Reference clock frequency #5 | 25 to 380 MHz | Specifies the reference clock #5 frequency. Range is:
|
Enable Reference clock #6 for FGT PMA | On/Off | Enable logical reference clock #6 for FGT PMA. This reference clock can also be shared by system PLL. The default value is Off. |
Reference clock frequency #6 | 25 to 380 MHz | Specifies the reference clock #6 frequency. Range is:
|
Enable Reference clock #7 for FGT PMA | On/Off | Enable logical reference clock #7 for FGT PMA. This reference clock can also be shared by system PLL. The default value is Off. |
Reference clock frequency #7 | 25 to 380 MHz | Specifies the reference clock #7 frequency. Range is:
|
Enable Reference clock #8 for FGT PMA | On/Off | Enable logical reference clock #8 for FGT PMA. This reference clock can also be shared by system PLL. The default value is Off. |
Reference clock frequency #8 | 25 to 380 MHz | Specifies the reference clock #8 frequency. Range is:
|
Enable Reference clock #9 for FGT PMA | On/Off | Enable logical reference clock #9 for FGT PMA. This reference clock can also be shared by system PLL. The default value is Off. |
Reference clock frequency #9 | 25 to 380 MHz | Specifies the reference clock #9 frequency. Range is:
|
FGT CDR Clock-out(s) | ||
Enable FGT CDR Output #0 | On/Off | Enables logical FGT CDR clock output #0. This must be enabled to configure FGT reference clock as a CDR clock output. The default value is Off. This feature is not supported in this release. |
Enable FGT CDR Output #1 | On/Off | Enables logical FGT CDR clock output #1. This must be enabled to configure FGT reference clock as a CDR clock output. The default value is Off. This feature is not supported in this release. |
FHT Reference clock(s) | ||
FHT Reference clock frequency #0 | 100 to 200 MHz | Specifies the FHT reference clock #0 frequency in MHz. |
FHT Reference clock frequency #1 | 100 to 200 MHz | Specifies the FHT reference clock #1 frequency in MHz. |
35 This mode is not currently supported