F-tile Architecture and PMA and FEC Direct PHY IP User Guide

ID 683872
Date 10/15/2021
Public

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3.5.4. Example of TX Parallel Data for PMA width = 64 (X=2)

The following data is specific to the X=2 case. N indicates the number of PMA lanes. For a given N, n can be from 0 --> N-1. N can be up to 8 for FGT, and up to 4 for FHT, and depends on the number of PMA lanes. Enable Double width transfer = 1. Refer to Table 1 for full variable definitions.

Table 62.  Example of TX Parallel Data for PMA width = 64 (X =2)
Condition Bits TX Parallel Data for n=0 Bits TX Parallel Data for n=1 ●● Bits TX Parallel Data for n=7
Second Stream 159 Write Enable for TX Core FIFO in Elastic Mode 319 Write Enable for TX Core FIFO in Elastic Mode ●● 1279 Write Enable for TX Core FIFO in Elastic Mode
151:120 TX Data (Upper Data Bits) 311:280 TX Data (Upper Data Bits) 1391:1240 TX Data (Upper Data Bits)
118 TX PMA Interface Data Valid 278 TX PMA Interface Data Valid 1238 TX PMA Interface Data Valid
111:80 TX Data (Lower Data Bits) 271:240 TX Data (Lower Data Bits) ●● 1231:1200 TX Data (Lower Data Bits)
First Stream 79 Write Enable for TX Core FIFO in Elastic Mode 239 Write Enable for TX Core FIFO in Elastic Mode 1199 Write Enable for TX Core FIFO in Elastic Mode
71:40 TX Data (Upper Data Bits) 231:200 TX Data (Upper Data Bits) 1191:1160 TX Data (Upper Data Bits)
38 TX PMA Interface Data Valid 198 TX PMA Interface Data Valid ●● 1158 TX PMA Interface Data Valid
31:0 TX Data (Lower Data Bits) 191:160 TX Data (Lower Data Bits) 1151:1120 TX Data (Lower Data Bits)

The following are the TX PMA Interface Data Valid signals for each of PMA Lanes, for each stream, in Table 62.

  • If PMA lanes n=0, for first stream data, data valid signal = tx_parallel_data [38]
  • If PMA lanes n=0, for second stream data, data valid signal = tx_parallel_data [118]
  • If PMA lanes n=1, for first stream data, data valid signal = tx_parallel_data [198]
  • If PMA lanes n=1, for second stream data, data valid signal = tx_parallel_data [278]