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Answers to Top FAQs
1. FPGA Simulation Basics
2. Siemens EDA QuestaSim* Simulator Support
3. Synopsys VCS* and VCS MX Support
4. Aldec Active-HDL and Riviera-PRO Support
5. Cadence Xcelium* Parallel Simulator Support
6. Quartus® Prime Pro Edition User Guide Third-party Simulation Archive
A. Quartus® Prime Pro Edition User Guides
1.1. FPGA Simulation Essential Elements
1.2. Overview of Simulation Tool Flow
1.3. Simulation Tool Flow
1.4. Supported Simulation Flows
1.5. Supported Hardware Description Languages
1.6. Supported Simulation Types
1.7. Supported Simulators
1.8. Post-Fit Simulation Support by FPGA Family
1.9. Automating Simulation with the Run Simulation Feature
1.10. FPGA Simulation Basics Revision History
1.9.2.1. Specifying Required Simulation Settings for Run Simulation (Batch Mode)
1.9.2.2. Optional Simulation Settings for Run Simulation (Batch Mode)
1.9.2.3. Launching Simulation with the Run Simulation Feature
1.9.2.4. Running RTL Simulation using Run Simulation
1.9.2.5. Output Directories and Files for Run Simulation
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1.3.3.1. The Quartus® Prime Simulation Library Compiler
The Quartus® Prime Simulation Library Compiler is an Quartus® Prime software GUI and command-line tool that generates simulation scripts. You can use these scripts to automatically compile the Quartus® Prime software simulation libraries for a given simulator, device family, and hardware description language (Verilog HDL or VHDL).
Note: For Questa* Intel® FPGA Edition, do not use the Simulation Library Compiler to compile the libraries in Questa* Intel® FPGA Edition. Instead, you must use the Questa* Intel® FPGA Edition precompiled libraries included with this simulator.
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