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Answers to Top FAQs
1. FPGA Simulation Basics
2. Siemens EDA QuestaSim* Simulator Support
3. Synopsys VCS* and VCS MX Support
4. Aldec Active-HDL and Riviera-PRO Support
5. Cadence Xcelium* Parallel Simulator Support
6. Quartus® Prime Pro Edition User Guide Third-party Simulation Archive
A. Quartus® Prime Pro Edition User Guides
1.1. FPGA Simulation Essential Elements
1.2. Overview of Simulation Tool Flow
1.3. Simulation Tool Flow
1.4. Supported Simulation Flows
1.5. Supported Hardware Description Languages
1.6. Supported Simulation Types
1.7. Supported Simulators
1.8. Post-Fit Simulation Support by FPGA Family
1.9. Automating Simulation with the Run Simulation Feature
1.10. FPGA Simulation Basics Revision History
1.9.2.1. Specifying Required Simulation Settings for Run Simulation (Batch Mode)
1.9.2.2. Optional Simulation Settings for Run Simulation (Batch Mode)
1.9.2.3. Launching Simulation with the Run Simulation Feature
1.9.2.4. Running RTL Simulation using Run Simulation
1.9.2.5. Output Directories and Files for Run Simulation
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1.4. Supported Simulation Flows
The Quartus® Prime software supports scripted and specialized simulation flows.
Simulation Flow | Description |
---|---|
Scripted Simulation Flows | Scripted simulation supports custom control of all aspects of simulation, such as custom compilation commands, or multipass simulation flows. Use a version-independent top-level simulation script that sources Quartus® Prime-generated IP simulation setup scripts. The Quartus® Prime software can generate a combined simulator setup script for all IP cores, for each supported simulator. |
Run Simulation | You can use the Run Simulation feature in the Quartus® Prime Pro Edition software to integrate your supported third-party EDA simulator and automate generation of simulator-specific files and setup scripts, compilation of simulation libraries, and launch of your simulation. |
Qrun Flow | The Qrun flow optionally creates simulation files, including the functional simulation model, and any testbench (or example design) for the QuestaSim* and Questa* Intel® FPGA Edition simulators only. The Qrun flow can automatically combine the compile, optimize, and simulate functions into a single step. |
Specialized Simulation Flows | Specialized simulation flows support various design scenarios:
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