P-tile Avalon® Memory-mapped Intel® FPGA IP for PCI Express* Design Example User Guide

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ID 683853
Date 3/28/2022
Public
Document Table of Contents
Document Table of Contents x
1. Design Example Overview 2. Endpoint Design Example 3. Current Limitations of the Design Examples 4. Quick Start Guide 5. P-Tile Avalon Memory-mapped Intel FPGA IP for PCI Express Design Example User Guide Archives A. Document Revision History for the P-Tile Avalon® Memory-mapped Intel FPGA IP for PCI Express Design Example User Guide
2. Endpoint Design Example x
2.1. Block Descriptions 2.2. Programming Model for the Design Example 2.3. Descriptor Format for the Design Example 2.4. DMA Operations Using the Design Example
2.1. Block Descriptions x
2.1.1. DMA Controller 2.1.2. Avalon-MM Address to PCIe Address Mapping 2.1.3. BAR Interpreter
2.1.1. DMA Controller x
2.1.1.1. Register Set 2.1.1.2. Deadlock Risk and Avoidance 2.1.1.3. Interrupts 2.1.1.4. Using the DMA Controller
2.4. DMA Operations Using the Design Example x
2.4.1. Read DMA Example 2.4.2. Write DMA Example
4. Quick Start Guide x
4.1. Design Components 4.2. Directory Structure 4.3. Generating the Design Example 4.4. Simulating the Design Example 4.5. Compiling the Design Example 4.6. Installing the Linux Kernel Driver 4.7. Running the Endpoint Design Example Application
1. Design Example Overview
2. Endpoint Design Example
3. Current Limitations of the Design Examples
4. Quick Start Guide
5. P-Tile Avalon Memory-mapped Intel FPGA IP for PCI Express Design Example User Guide Archives
A. Document Revision History for the P-Tile Avalon® Memory-mapped Intel FPGA IP for PCI Express Design Example User Guide

4.4. Simulating the Design Example

Figure 8. Procedure
  1. Change to the testbench simulation directory, intel_pcie_ptile_avmm_0_example_design\pcie_ed_tb.
  2. Run the simulation script for VCS. Refer to the table below.
  3. Analyze the results.
Note: P-Tile does not support parallel PIPE simulations.
Note:
Table 8.  Steps to Run Simulation
Simulator Working Directory Instructions
VCS* <example_design>/pcie_ed_tb/pcie_ed_tb/sim/synopsys/vcs
  1. sh vcs_setup.sh USER_DEFINED_COMPILE_OPTIONS="" USER_DEFINED_ELAB_OPTIONS="-xlrm\ uniq_prior_final" USER_DEFINED_SIM_OPTIONS=""
  2. A successful simulation ends with the following message, "Simulation stopped due to successful completion!"
Note:
To run a simulation in interactive mode, use the following steps: (if you already generated a simv executable in non-interactive mode, delete the simv and simv.diadir)
  1. Open the vcs_setup.sh file and add a debug option to the VCS command: vcs -debug_access+r
  2. Compile the design example: sh vcs_setup.sh USER_DEFINED_ELAB_OPTIONS="-xlrm\ uniq_prior_final" SKIP_SIM=1
  3. Start the simulation in interactive mode: simv -gui &
The DMA testbench completes the following tasks:
  1. Writes to the Endpoint memory using the DUT Endpoint non-bursting Avalon® -MM master interface.
  2. Reads from Endpoint memory using the DUT Endpoint non-bursting Avalon® -MM master interface.
  3. Verifies the data using the shmem_chk_ok task.
  4. Writes to the Endpoint DMA controller, instructing the DMA controller to perform a MRd request to the PCIe* address space in host memory.
  5. Writes to the Endpoint DMA controller, instructing the DMA controller to perform a MWr request to PCIe* address space in host memory. This MWr uses the data from the previous MRd.
  6. Verifies the data using the shmem_chk_ok task.

The simulation reports, "Simulation stopped due to successful completion" if no errors occur.

Figure 9. Partial Transcript from Successful Simulation Testbench

The following figure shows the behavior of Data Mover interface signals during a read data transfer followed by a write data transfer.

Figure 10. Behavior of Read Data Mover and Write Data Mover Interface Signals During Data Transfers

As shown in the simulation waveforms, the Read Data Mover's data transfer happened around 200 us, and the Write Data Mover's data transfer happened around 204 us.

Test Case for the Endpoint Gen4 x16 Design Example

The test case for this design example is in the file intel_pcie_ptile_avmm_0_example_design\pcie_ed_tb\ip\pcie_ed_tb\dut_pcie_tb_ip\intel_pcie_ptile_tbed_100\sim\altpcietb_bfm_rp_gen4_x16.sv.

The task to run the test is called avmmdma_rdwr_512IP_test.

The test case consists of:

For the Read Data Mover:
  1. Create a Ramp in Buffer_0.
  2. Create an associated descriptor table targeting Buffer_0.
  3. Create a descriptor for the read descriptor table (created in step 2) and append a descriptor to write to the host memory when DMA is done.
  4. Send the descriptor (created in step 3) to the DMA controller through the BAM Interface.
  5. The DMA Controller processes the descriptor then reads the descriptor tables. At this time, all descriptors are fetched and placed inside the DMA Controller FIFO.
  6. The Read Data Mover issues a read command to read data from Buffer_0 and send it to the internal RAM.
  7. The Read Data Mover issues a MWr for the Status bit.
For the Write Data Mover:
  1. Create an empty Buffer_1.
  2. Create an associated descriptor table targeting Buffer_1.
  3. Create a descriptor for the read descriptor table (created in step 2) and append a descriptor to write to the host memory when DMA is done.
  4. Send the descriptor (created in step 3) to the DMA controller through the BAM Interface.
  5. The DMA Controller processes the descriptor then reads the descriptor tables. At this time, all descriptors are fetched and placed inside the DMA Controller FIFO.
  6. The Write Data Mover issues a read command to read data from internal RAM and send it to the PCIe host memory.
  7. The Write Data Mover issues a MWr for the Status bit.

The test case then compares the contents of Buffer_0 and Buffer_1. If they match, the test passes.

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