P-tile Avalon® Memory-mapped Intel® FPGA IP for PCI Express* Design Example User Guide

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ID 683853
Date 3/28/2022
Public
Document Table of Contents
Document Table of Contents x
1. Design Example Overview 2. Endpoint Design Example 3. Current Limitations of the Design Examples 4. Quick Start Guide 5. P-Tile Avalon Memory-mapped Intel FPGA IP for PCI Express Design Example User Guide Archives A. Document Revision History for the P-Tile Avalon® Memory-mapped Intel FPGA IP for PCI Express Design Example User Guide
2. Endpoint Design Example x
2.1. Block Descriptions 2.2. Programming Model for the Design Example 2.3. Descriptor Format for the Design Example 2.4. DMA Operations Using the Design Example
2.1. Block Descriptions x
2.1.1. DMA Controller 2.1.2. Avalon-MM Address to PCIe Address Mapping 2.1.3. BAR Interpreter
2.1.1. DMA Controller x
2.1.1.1. Register Set 2.1.1.2. Deadlock Risk and Avoidance 2.1.1.3. Interrupts 2.1.1.4. Using the DMA Controller
2.4. DMA Operations Using the Design Example x
2.4.1. Read DMA Example 2.4.2. Write DMA Example
4. Quick Start Guide x
4.1. Design Components 4.2. Directory Structure 4.3. Generating the Design Example 4.4. Simulating the Design Example 4.5. Compiling the Design Example 4.6. Installing the Linux Kernel Driver 4.7. Running the Endpoint Design Example Application
1. Design Example Overview
2. Endpoint Design Example
3. Current Limitations of the Design Examples
4. Quick Start Guide
5. P-Tile Avalon Memory-mapped Intel FPGA IP for PCI Express Design Example User Guide Archives
A. Document Revision History for the P-Tile Avalon® Memory-mapped Intel FPGA IP for PCI Express Design Example User Guide

2.4.1. Read DMA Example

A Read DMA transfers data from the PCIe address space (system memory) to the Avalon-MM address space. It sends Memory Read TLPs upstream, and writes the completion data to local memory in the Avalon-MM address space using the Read Data Mover's Avalon® -MM write master interface.

The sequence of steps the example design follows to do a Read DMA is:
  1. Prepare a table of descriptors (padded to 512-bit each) to perform the Read operation and put the table into the system memory.
  2. Using the BAM, send one descriptor from software containing the address of the descriptor table to the DMA Controller, which forwards it to the Read Data Mover.
  3. The Read Data Mover fetches the descriptor table and puts it in a FIFO inside the DMA Controller.
  4. The DMA Controller outputs these descriptors to the Read Data Mover based on the readiness of the Read Data Mover (indicated by an asserted rddm_desc_ready_o or rddm_prio_ready_o signal).
  5. The Read Data Mover processes the descriptors by fetching data from the system memory, and writing it to the appropriate Avalon® -MM memory.
  6. The last descriptor processed by the Read Data Mover points to an immediate write descriptor (i.e, a descriptor where the data to be written is inside the descriptor itself) in the system memory. This descriptor's destination address is the Avalon® memory address of the DMA Controller's Write Data Mover port. The Read Data Mover fetches this descriptor from system memory and transfers it to the DMA Controller's Write Data Mover Avalon® address.
  7. The Write Data Mover uses the descriptor from Step 6 to perform an immediate write to the system memory indicating the completion of the Read Data Mover’s data processing.
Level Two Title