P-tile Avalon® Memory-mapped Intel® FPGA IP for PCI Express* Design Example User Guide

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ID 683853
Date 3/28/2022
Public
Document Table of Contents
Document Table of Contents x
1. Design Example Overview 2. Endpoint Design Example 3. Current Limitations of the Design Examples 4. Quick Start Guide 5. P-Tile Avalon Memory-mapped Intel FPGA IP for PCI Express Design Example User Guide Archives A. Document Revision History for the P-Tile Avalon® Memory-mapped Intel FPGA IP for PCI Express Design Example User Guide
2. Endpoint Design Example x
2.1. Block Descriptions 2.2. Programming Model for the Design Example 2.3. Descriptor Format for the Design Example 2.4. DMA Operations Using the Design Example
2.1. Block Descriptions x
2.1.1. DMA Controller 2.1.2. Avalon-MM Address to PCIe Address Mapping 2.1.3. BAR Interpreter
2.1.1. DMA Controller x
2.1.1.1. Register Set 2.1.1.2. Deadlock Risk and Avoidance 2.1.1.3. Interrupts 2.1.1.4. Using the DMA Controller
2.4. DMA Operations Using the Design Example x
2.4.1. Read DMA Example 2.4.2. Write DMA Example
4. Quick Start Guide x
4.1. Design Components 4.2. Directory Structure 4.3. Generating the Design Example 4.4. Simulating the Design Example 4.5. Compiling the Design Example 4.6. Installing the Linux Kernel Driver 4.7. Running the Endpoint Design Example Application
1. Design Example Overview
2. Endpoint Design Example
3. Current Limitations of the Design Examples
4. Quick Start Guide
5. P-Tile Avalon Memory-mapped Intel FPGA IP for PCI Express Design Example User Guide Archives
A. Document Revision History for the P-Tile Avalon® Memory-mapped Intel FPGA IP for PCI Express Design Example User Guide

2.2. Programming Model for the Design Example

The programming model for the DMA example design performs the following steps:
  1. In system memory, prepare a contiguous set of descriptors. The last of these descriptors is an immediate write descriptor, with the destination address set to some special system memory status location. The descriptor table must start on a 64-byte aligned address. Even though each descriptor is only about 174-bit long, 512 bits are reserved for each descriptor. The descriptors are LSB-aligned in that 512-bit field.
  2. In system memory, prepare one more descriptor which reads from the beginning of the descriptors from Step 1 and writes them to a special FIFO Avalon® -MM address in FPGA.
  3. Write the descriptor in Step 2 to the same special FIFO Avalon® -MM address by:
    1. Writing one dword at a time, ending with the most significant dword.
    2. Writing three dwords of padding and the entire descriptor for a total of eight dwords (the descriptor takes up only five dwords, but CPUs do not typically support single-TLP, five-dword writes).
  4. Poll the special status location in system memory to see if the final immediate write has occurred, indicating the DMA completion.
Level Two Title