P-tile Avalon® Memory-mapped Intel® FPGA IP for PCI Express* Design Example User Guide

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ID 683853
Date 3/28/2022
Public
Document Table of Contents
Document Table of Contents x
1. Design Example Overview 2. Endpoint Design Example 3. Current Limitations of the Design Examples 4. Quick Start Guide 5. P-Tile Avalon Memory-mapped Intel FPGA IP for PCI Express Design Example User Guide Archives A. Document Revision History for the P-Tile Avalon® Memory-mapped Intel FPGA IP for PCI Express Design Example User Guide
2. Endpoint Design Example x
2.1. Block Descriptions 2.2. Programming Model for the Design Example 2.3. Descriptor Format for the Design Example 2.4. DMA Operations Using the Design Example
2.1. Block Descriptions x
2.1.1. DMA Controller 2.1.2. Avalon-MM Address to PCIe Address Mapping 2.1.3. BAR Interpreter
2.1.1. DMA Controller x
2.1.1.1. Register Set 2.1.1.2. Deadlock Risk and Avoidance 2.1.1.3. Interrupts 2.1.1.4. Using the DMA Controller
2.4. DMA Operations Using the Design Example x
2.4.1. Read DMA Example 2.4.2. Write DMA Example
4. Quick Start Guide x
4.1. Design Components 4.2. Directory Structure 4.3. Generating the Design Example 4.4. Simulating the Design Example 4.5. Compiling the Design Example 4.6. Installing the Linux Kernel Driver 4.7. Running the Endpoint Design Example Application
1. Design Example Overview
2. Endpoint Design Example
3. Current Limitations of the Design Examples
4. Quick Start Guide
5. P-Tile Avalon Memory-mapped Intel FPGA IP for PCI Express Design Example User Guide Archives
A. Document Revision History for the P-Tile Avalon® Memory-mapped Intel FPGA IP for PCI Express Design Example User Guide

2.3. Descriptor Format for the Design Example

The Read and Write Data Movers uses descriptors to transfer data. The descriptor format is fixed and specified below:

Table 6.  Descriptor Format for Data Movers
Signals Description (for rddm_desc_data_i or wrdm_desc_data_i) Read Data Mover Write Data Mover
[173:160]: reserved N/A N/A
[159:152]: descriptor ID ID of the descriptor ID of the descriptor
[151:149]: application-specific

Application-specific bits.

Example of an Intel application is provided below.

Application-specific bits.

Example of an Intel application is provided below.
[148]: single destination When the single destination bit is set, the same destination address is used for all the transfers. If the bit is not set, the address increments for each transfer. N/A
[147]: single source N/A When the single source bit is set, the same source address is used for all the transfers. If the bit is not set, the address increments for each transfer. Note that in single source mode, the PCIe address and Avalon-MM address must be 64-byte aligned.
[146]: immediate N/A

When set, the immediate bit indicates immediate writes. Immediate writes of one or two dwords are supported.

For immediate transfers, bits [31:0] or [63:0] contain the payload for one- or two-dword transfers respectively. The two-dword immediate writes cannot cross a 4k boundary.

This can be used for MSI/MSI-X for example.
[145:128]: transfer size

Number of dwords to transfer.

Number of dwords to transfer (up to 8192 dwords, or 32 kB, per descriptor).

[127:64]: destination address

Avalon-MM address

 PCIe Address
[63:0]: source address PCIe Address Avalon-MM address

Application-Specific Bits

Three application-specific bits (bits [151:149] ) from the Write Data Mover and Read Data Mover Status Avalon-ST Source interfaces control when interrupts are generated.

Table 7.  Encodings for Application-Specific Bits
Bit [151] Bit [150] Bit [149] Action
0 1 1 Interrupt always
0 1 0 Interrupt if error
0 0 1 No interrupt
0 0 0 No interrupt and drop status word

The External DMA Controller makes the decision whether to drop the status word and whether to generate an interrupt as soon as it receives the status word from the Data Mover. When the generation of an interrupt is requested, and the corresponding RI or WI register does enable interrupts, the DMA Controller generates the interrupt. It does so by queuing an immediate write to the Write Data Mover's descriptor queue (specified in the corresponding interrupt control register) using the MSI address and message data provided in that register.

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