P-tile Avalon® Memory-mapped Intel® FPGA IP for PCI Express* Design Example User Guide

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ID 683853
Date 3/28/2022
Public
Document Table of Contents
Document Table of Contents x
1. Design Example Overview 2. Endpoint Design Example 3. Current Limitations of the Design Examples 4. Quick Start Guide 5. P-Tile Avalon Memory-mapped Intel FPGA IP for PCI Express Design Example User Guide Archives A. Document Revision History for the P-Tile Avalon® Memory-mapped Intel FPGA IP for PCI Express Design Example User Guide
2. Endpoint Design Example x
2.1. Block Descriptions 2.2. Programming Model for the Design Example 2.3. Descriptor Format for the Design Example 2.4. DMA Operations Using the Design Example
2.1. Block Descriptions x
2.1.1. DMA Controller 2.1.2. Avalon-MM Address to PCIe Address Mapping 2.1.3. BAR Interpreter
2.1.1. DMA Controller x
2.1.1.1. Register Set 2.1.1.2. Deadlock Risk and Avoidance 2.1.1.3. Interrupts 2.1.1.4. Using the DMA Controller
2.4. DMA Operations Using the Design Example x
2.4.1. Read DMA Example 2.4.2. Write DMA Example
4. Quick Start Guide x
4.1. Design Components 4.2. Directory Structure 4.3. Generating the Design Example 4.4. Simulating the Design Example 4.5. Compiling the Design Example 4.6. Installing the Linux Kernel Driver 4.7. Running the Endpoint Design Example Application
1. Design Example Overview
2. Endpoint Design Example
3. Current Limitations of the Design Examples
4. Quick Start Guide
5. P-Tile Avalon Memory-mapped Intel FPGA IP for PCI Express Design Example User Guide Archives
A. Document Revision History for the P-Tile Avalon® Memory-mapped Intel FPGA IP for PCI Express Design Example User Guide

4.7. Running the Endpoint Design Example Application

For link stability when running the design example on the Intel® Stratix® 10 DX FPGA Development Kit or the Intel® Agilex™ F-Series FPGA Development Kit, set the PCIe refclk switch to select the common refclk from the PCIe Edge Connector.
  • For the Intel® Stratix® 10 DX FPGA Development Kit, set SW14 to the OFF position to select the common refclk with the PCIe Host.
  • For the Intel® Agilex™ F-Series FPGA Development Kit, set SW7.1 to the OFF position to select the common refclk with the PCIe Host.

Here are the test operations you can perform on the P-Tile Avalon® Memory-mapped design example:

Table 9.  Test Operations Supported by the P-Tile Avalon® Memory-mapped PCIe Design Example
Operations Required BAR Supported by P-Tile Avalon® -MM PCIe Design Example
0: Link test - 100 writes and reads 2 Yes
1: Write memory space 2 Yes
2: Read memory space 2 Yes
3: Write configuration space N/A Yes
4: Read configuration space N/A Yes
5: Change BAR N/A Yes
6: Change device N/A Yes
7: Enable SR-IOV N/A No
8: Do a link test for every enabled virtual function belonging to the current device N/A No
9: Perform DMA 0 Yes
10: Quit program N/A Yes
To run a DMA test:
  1. Navigate to ./software/user/example under the design example directory.
  2. Compile the design example application:

    $ make

  3. Run the test:

    $ sudo ./intel_fpga_pcie_link_test

    You can run the Intel FPGA IP PCIe link test in manual or automatic mode.
    • In automatic mode, the application automatically selects the device. The test selects the Intel® Stratix® 10 DX or Intel® Agilex™ PCIe device with the lowest BDF by matching the Vendor ID. The test also selects the lowest available BAR.
    • In manual mode, the test queries you for the bus, device, and function number and BAR.

    For the Intel® Stratix® 10 DX or Intel® Agilex™ Development Kit, you can determine the BDF by typing the following command:

    $ lspci -d 1172

  4. For example, enter 0 to select Automatically select a device.
  5. Enter 9 to perform the DMA test.

  6. Enter 0 to run DMA. Then enter 0 again to run an infinite DMA loop test.
  7. The DMA test can be stopped by hitting the ESC key. Here is a sample transcript of the results:

    Note: The throughput numbers above are for a Gen3 x16 design example.
  8. Enter 6 to return to the main menu.
  9. Enter 5 to change the BAR. Then enter 2 to select BAR2.
  10. Enter 0 to start the Link test - 100 writes and reads.
  11. The results below show zero write and read error as well as zero Dword mismatch.

  12. Enter 5 to change the BAR. Then enter 4 to select BAR4.
  13. Enter 4 to Read the configuration space.
  14. Enter 0x0 to read out the Vendor ID.

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