P-tile Avalon® Memory-mapped Intel® FPGA IP for PCI Express* Design Example User Guide

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ID 683853
Date 3/28/2022
Public
Document Table of Contents
Document Table of Contents x
1. Design Example Overview 2. Endpoint Design Example 3. Current Limitations of the Design Examples 4. Quick Start Guide 5. P-Tile Avalon Memory-mapped Intel FPGA IP for PCI Express Design Example User Guide Archives A. Document Revision History for the P-Tile Avalon® Memory-mapped Intel FPGA IP for PCI Express Design Example User Guide
2. Endpoint Design Example x
2.1. Block Descriptions 2.2. Programming Model for the Design Example 2.3. Descriptor Format for the Design Example 2.4. DMA Operations Using the Design Example
2.1. Block Descriptions x
2.1.1. DMA Controller 2.1.2. Avalon-MM Address to PCIe Address Mapping 2.1.3. BAR Interpreter
2.1.1. DMA Controller x
2.1.1.1. Register Set 2.1.1.2. Deadlock Risk and Avoidance 2.1.1.3. Interrupts 2.1.1.4. Using the DMA Controller
2.4. DMA Operations Using the Design Example x
2.4.1. Read DMA Example 2.4.2. Write DMA Example
4. Quick Start Guide x
4.1. Design Components 4.2. Directory Structure 4.3. Generating the Design Example 4.4. Simulating the Design Example 4.5. Compiling the Design Example 4.6. Installing the Linux Kernel Driver 4.7. Running the Endpoint Design Example Application
1. Design Example Overview
2. Endpoint Design Example
3. Current Limitations of the Design Examples
4. Quick Start Guide
5. P-Tile Avalon Memory-mapped Intel FPGA IP for PCI Express Design Example User Guide Archives
A. Document Revision History for the P-Tile Avalon® Memory-mapped Intel FPGA IP for PCI Express Design Example User Guide

2.1.1.3. Interrupts

Two application specific bits (bits [13:12]) of the status words from the Write Data Mover and Read Data Mover Status Avalon® -ST Source interfaces control when interrupts are generated.

Table 5.  Interrupts Control
Bit [13] Bit [12] Action
1 1 Interrupt always
1 0 Interrupt if error
0 1 No interrupt
0 0 No interrupt and drop status word (i.e, do not even write it to the WS or RS status queues)

The DMA Controller makes the decision whether to drop the status word and whether to generate an interrupt as soon as it receives the status word from the Data Mover. When generation of an interrupt is requested, and the corresponding RI or WI register does enable interrupts, the DMA Controller generates the interrupt. It does so by queuing an immediate write to the Write Data Mover's descriptor queue specified in the corresponding interrupt control register using the MSI address and message data provided in that register.You need to make sure that space is always available in the targeted Write Data Mover descriptor queue at any time when an interrupt may get generated. You can do so most easily by using the priority queue only for MSIs.

Setting the interrupt control bits in the immediate write descriptors that the DMA Controller creates to generate MSI interrupts to "No interrupt and drop status word" can avoid an infinite loop of interrupts.

Level Two Title