Streaming DMA Accelerator Functional Unit User Guide: Intel® Programmable Acceleration Card with Intel® Arria® 10 GX FPGA

Download PDF
ID 683840
Date 3/06/2020
Public
Document Table of Contents
Document Table of Contents x
1. About this Document 2. Streaming DMA AFU Description 3. Memory Map and Address Spaces 4. Software Programming Model 5. Running the AFU Example 6. Compiling the Accelerator Function (AF) 7. Simulating the AFU Example 8. Streaming DMA AFU User Guide Archives 9. Document Revision History for Streaming DMA Accelerator Functional Unit User Guide A. Enabling Hugepages
1. About this Document x
1.1. Intended Audience 1.2. Conventions 1.3. Acronyms 1.4. Acceleration Glossary
2. Streaming DMA AFU Description x
2.1. Hardware Subsystems 2.2. Streaming DMA Test System 2.3. Memory-to-Stream DMA BBB 2.4. Stream-to-Memory DMA BBB
3. Memory Map and Address Spaces x
3.1. Streaming DMA AFU Memory Map 3.2. Memory-to-Stream DMA BBB Memory Map 3.3. Stream-to-Memory DMA BBB Memory Map 3.4. Device Feature Header Linked-list
5. Running the AFU Example x
5.1. Optimization for Improved DMA Performance
1. About this Document
2. Streaming DMA AFU Description
3. Memory Map and Address Spaces
4. Software Programming Model
5. Running the AFU Example
6. Compiling the Accelerator Function (AF)
7. Simulating the AFU Example
8. Streaming DMA AFU User Guide Archives
9. Document Revision History for Streaming DMA Accelerator Functional Unit User Guide
A. Enabling Hugepages

3.3. Stream-to-Memory DMA BBB Memory Map

The S2M DMA BBB memory map provides the address offsets of all the locations within the BBB. The following streaming DMA AFU registers reside at offset 0x200 in the MMIO address space.
Table 6.  Stream-to-Memory DMA BBB Memory Map
Byte Address Offsets Slave Name Span in Bytes Description
0x00 S2M DMA BBB DFH 0x40 Device feature header for the S2M DMA BBB. This DFH points to 0x100 as the next DFH offset.
0x40 S2M DMA Dispatcher CSR 0x20

Control port for the mSGDMA within the stream-to-memory DMA BBB.

The driver accesses this location to control the DMA or query its status.
0x80 S2M DMA Response 0x8 Response port for the mSGDMA within the stream-to-memory DMA BBB. The driver reads this port to determine how much data was streamed to the memory.
0x80 S2M DMA Descriptor Frontend CSR 0X40 Control port for the S2M DMA descriptor frontend. The driver accesses this location to control the descriptor frontend or query its status.
Level Two Title