Streaming DMA Accelerator Functional Unit User Guide: Intel® Programmable Acceleration Card with Intel® Arria® 10 GX FPGA

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ID 683840
Date 3/06/2020
Public
Document Table of Contents
Document Table of Contents x
1. About this Document 2. Streaming DMA AFU Description 3. Memory Map and Address Spaces 4. Software Programming Model 5. Running the AFU Example 6. Compiling the Accelerator Function (AF) 7. Simulating the AFU Example 8. Streaming DMA AFU User Guide Archives 9. Document Revision History for Streaming DMA Accelerator Functional Unit User Guide A. Enabling Hugepages
1. About this Document x
1.1. Intended Audience 1.2. Conventions 1.3. Acronyms 1.4. Acceleration Glossary
2. Streaming DMA AFU Description x
2.1. Hardware Subsystems 2.2. Streaming DMA Test System 2.3. Memory-to-Stream DMA BBB 2.4. Stream-to-Memory DMA BBB
3. Memory Map and Address Spaces x
3.1. Streaming DMA AFU Memory Map 3.2. Memory-to-Stream DMA BBB Memory Map 3.3. Stream-to-Memory DMA BBB Memory Map 3.4. Device Feature Header Linked-list
5. Running the AFU Example x
5.1. Optimization for Improved DMA Performance
1. About this Document
2. Streaming DMA AFU Description
3. Memory Map and Address Spaces
4. Software Programming Model
5. Running the AFU Example
6. Compiling the Accelerator Function (AF)
7. Simulating the AFU Example
8. Streaming DMA AFU User Guide Archives
9. Document Revision History for Streaming DMA Accelerator Functional Unit User Guide
A. Enabling Hugepages

2.3. Memory-to-Stream DMA BBB

The Memory-to-Stream (M2S) DMA BBB reads data from a buffer stored in memory and converts it into an Avalon® -ST source stream. The buffer must be aligned to 64 bytes. The M2S DMA BBB is configured to handle up to a 1 gigabyte (GB) transfer size, which requires a buffer to be allocated with a 1 GB hugepage to ensure it resides in continuous physical memory. The M2S DMA BBB can also transfer payloads up to 4 KB and 2 MB of size depending on the page size used when allocating the pinned memory.

The M2S DMA BBB streaming interface supports packet generation by exposing the start-of-packet (SOP), end-of-packet (EOP), and empty signals. Your host application can optionally instruct the streaming DMA driver to generate packetized data. If you enable the packetized data, then the empty signal conveys the number of bytes at the end of a transfer that are invalid when the EOP signal is asserted. For example, a DMA transfer of 4100 bytes contains 65 beats of streaming data with SOP asserted during the first beat and EOP asserted during the last beat. The empty signal is set to 60 (0x3C) on the last streaming beat. Since the first 64 beats transfer 64 bytes each, the last beat only contains four valid bytes (first four bytes out of 64 are valid).
Figure 3. M2S DMA BBB Platform Designer System

The components in the M2S DMA BBB Platform Designer system implement the following functions:
  • M2S DMA BBB DFH—stores the 64-bit device feature header (DFH) for the M2S DMA BBB. The host driver scans the hardware that is searching for the DMA BBBs. The M2S DMA BBB DFH is setup to point to the next DFH at offset 0x100.

  • Dispatcher—buffers descriptors before issuing read transfer commands to the read master.

  • Read Master—accepts commands from the dispatcher and reads from memory and converts the data to an Avalon® -ST stream. The data leaving the streaming port can be accompanied by streaming sideband signaling for SOP, EOP, and empty signals. If you require the stream to support non-multiples of 64 bytes, then you must request the driver to send packetized data. Therefore, if the last beat is not 64 bytes in size, then the empty signal informs your downstream hardware about the invalid bytes. Only the last beat can contain invalid bytes, all other beats must be 64 bytes in size which is defined by the Avalon® -ST specification.

  • Pipeline Bridge—To improve the maximum operating frequency (Fmax) of the M2S DMA BBB, the following pipeline bridge components have been added:
    • MMIO CSR Pipeline Bridge: Connects to all the Avalon® slaves inside the DMA BBB (Descriptor Frontend, Dispatcher, DMA BBB DFH) and span an address range of 0x100.
    • Host Reads Pipeline Bridge: Reads data from host memory. Added between the Read Master and host memory.
    • FPGA Memory Reads Pipeline Bridge: Reads data from FPGA memory. Added between the Read Master and FPGA memory.
    If your design does not require the M2S DMA BBB to connect to local FPGA memory, then export the pipeline bridge master interface and ground all of its master inputs.
  • Descriptor Frontend—fetches transfer descriptors from the host memory and overwrites them with the status information after the transfer completes.
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