Streaming DMA Accelerator Functional Unit User Guide: Intel® Programmable Acceleration Card with Intel® Arria® 10 GX FPGA

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ID 683840
Date 3/06/2020
Public
Document Table of Contents
Document Table of Contents x
1. About this Document 2. Streaming DMA AFU Description 3. Memory Map and Address Spaces 4. Software Programming Model 5. Running the AFU Example 6. Compiling the Accelerator Function (AF) 7. Simulating the AFU Example 8. Streaming DMA AFU User Guide Archives 9. Document Revision History for Streaming DMA Accelerator Functional Unit User Guide A. Enabling Hugepages
1. About this Document x
1.1. Intended Audience 1.2. Conventions 1.3. Acronyms 1.4. Acceleration Glossary
2. Streaming DMA AFU Description x
2.1. Hardware Subsystems 2.2. Streaming DMA Test System 2.3. Memory-to-Stream DMA BBB 2.4. Stream-to-Memory DMA BBB
3. Memory Map and Address Spaces x
3.1. Streaming DMA AFU Memory Map 3.2. Memory-to-Stream DMA BBB Memory Map 3.3. Stream-to-Memory DMA BBB Memory Map 3.4. Device Feature Header Linked-list
5. Running the AFU Example x
5.1. Optimization for Improved DMA Performance
1. About this Document
2. Streaming DMA AFU Description
3. Memory Map and Address Spaces
4. Software Programming Model
5. Running the AFU Example
6. Compiling the Accelerator Function (AF)
7. Simulating the AFU Example
8. Streaming DMA AFU User Guide Archives
9. Document Revision History for Streaming DMA Accelerator Functional Unit User Guide
A. Enabling Hugepages

9. Document Revision History for Streaming DMA Accelerator Functional Unit User Guide

Document Version Intel Acceleration Stack Version Changes
2020.03.06 1.2.1 (supported with Intel® Quartus® Prime Pro Edition Edition 19.2)
  • Added new appendix section Enabling Hugepages.
  • Updated the Figure: Streaming DMA Test System Block Diagram.
  • Updated the Figure: M2S DMA BBB Platform Designer System.
  • Updated the Figure: S2M DMA BBB Platform Designer System.
  • Updated the following in section Memory Map and Address Spaces:
    • Added DMA descriptor view information
    • Updated Figure: Streaming DMA AFU Memory Views
  • Added APIs and description table in section Software Programming Model.
  • Updated a command to generate the design build directory in section Compiling the Accelerator Function (AF).
  • Added a note in section Simulating the AFU Example to clarify the successful execution of the host application transfer.
2018.12.04 1.2 (supported with Intel® Quartus® Prime Pro Edition 17.1.1)
  • Updated the Running the AFU Example and Simulating the AFU Example steps.
  • Replaced the Write Response Bridge with the Far Reach Avalon-MM Bridge.
  • Added a new section NUMA Optimization.
  • Added a new chapter: Streaming DMA AFU User Guide Archives.
2018.08.06 1.1 (supported with Intel® Quartus® Prime Pro Edition 17.1.1) Initial release.
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