Streaming DMA Accelerator Functional Unit User Guide: Intel® Programmable Acceleration Card with Intel® Arria® 10 GX FPGA

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ID 683840
Date 3/06/2020
Public
Document Table of Contents
Document Table of Contents x
1. About this Document 2. Streaming DMA AFU Description 3. Memory Map and Address Spaces 4. Software Programming Model 5. Running the AFU Example 6. Compiling the Accelerator Function (AF) 7. Simulating the AFU Example 8. Streaming DMA AFU User Guide Archives 9. Document Revision History for Streaming DMA Accelerator Functional Unit User Guide A. Enabling Hugepages
1. About this Document x
1.1. Intended Audience 1.2. Conventions 1.3. Acronyms 1.4. Acceleration Glossary
2. Streaming DMA AFU Description x
2.1. Hardware Subsystems 2.2. Streaming DMA Test System 2.3. Memory-to-Stream DMA BBB 2.4. Stream-to-Memory DMA BBB
3. Memory Map and Address Spaces x
3.1. Streaming DMA AFU Memory Map 3.2. Memory-to-Stream DMA BBB Memory Map 3.3. Stream-to-Memory DMA BBB Memory Map 3.4. Device Feature Header Linked-list
5. Running the AFU Example x
5.1. Optimization for Improved DMA Performance
1. About this Document
2. Streaming DMA AFU Description
3. Memory Map and Address Spaces
4. Software Programming Model
5. Running the AFU Example
6. Compiling the Accelerator Function (AF)
7. Simulating the AFU Example
8. Streaming DMA AFU User Guide Archives
9. Document Revision History for Streaming DMA Accelerator Functional Unit User Guide
A. Enabling Hugepages

2.1. Hardware Subsystems

The Streaming DMA AFU accesses the host memory through the FPGA Interface Unit (FIU) and the local SDRAM directly. In practice the streaming DMAs typically only need to be connect to the FIU to access host memory. The streaming DMAs can access up to 256 TB of local memory.

You can use the streaming DMA AFU to perform the following data transfer:
  • Host memory to FPGA stream
  • FPGA stream to host memory
  • Local FPGA memory to FPGA stream 1
  • FPGA stream to local FPGA memory1

The Platform Designer system implements most part of the streaming DMA AFU, M2S and S2M DMA BBBs.

The Streaming DMA AFU implemented in the Platform Designer system can be found in the following location: 
$OPAE_PLATFORM_ROOT/hw/samples/streaming_dma_afu/hw/rtl/<device>/
You can find the two DMA BBBs in the following location:
  • S2M DMA BBB: 
    $OPAE_PLATFORM_ROOT/hw/samples/streaming_dma_afu/hw/rtl/stream_to_memory_dma_bbb
  • M2S DMA BBB: 
    $OPAE_PLATFORM_ROOT/hw/samples/streaming_dma_afu/hw/rtl/memory_to_stream_dma_bbb
Figure 1. High Level System Diagram

The streaming DMA AFU includes the following modules that connect to the FIU:
  • Memory-Mapped IO (MMIO) Decode Logic—detects MMIO read and write transactions and separates them from the CCI-P RX channel 0 that they arrive from. This ensures that MMIO traffic never reaches the MPF BBB and is serviced by an independent MMIO command channel.
  • MPF BBB—ensures that reads issued by the M2S DMA BBB are returned in the order that they were issued. The streaming DMA BBBs use the Avalon-MM protocol which requires the read data to return in-order.
  • CCI-P to Avalon® -MM Adapter—translates MMIO accesses to Avalon® -MM read and write transactions. This module also receives Avalon® -MM read and write transactions from the streaming DMA BBBs and converts them to CCI-P transactions that are issued to the host.
  • Streaming DMA Test System—a wrapper around the two streaming DMA BBBs and includes pattern checker and generator components. This module exposes Avalon® -MM master and slave interfaces that connect to the CCI-P to Avalon-MM adapter.
1 Supported in a future release of the Intel® Acceleration Stack.
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