AN 900: Intel® Arria 10 DisplayPort 8K RX-only Design

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ID 683799
Date 7/02/2021
Public
Document Table of Contents
Document Table of Contents x
1. Intel® Arria® 10 DisplayPort 8K RX-only Design
1. Intel® Arria® 10 DisplayPort 8K RX-only Design x
1.1. Design Components 1.2. Clocking Scheme 1.3. Top Level Interface Signals 1.4. Quick Start Guide 1.5. Creating the RX-only Design 1.6. Document Revision History for AN 900: Intel® Arria® 10 DisplayPort 8K RX-only Design
1.4. Quick Start Guide x
1.4.1. Hardware and Software Requirements 1.4.2. Directory Structure 1.4.3. Compiling the Design 1.4.4. Running the Design on Hardware 1.4.5. Design Debug Features
1.4.3. Compiling the Design x
1.4.3.1. Regenerating and Downloading ELF File
1.4.5. Design Debug Features x
1.4.5.1. Main Stream Attribute (MSA) Information 1.4.5.2. Auxiliary Channel Traffic Monitor 1.4.5.3. Signal Tap Logic Analyzer 1.4.5.4. Onboard User LED Functions
1.5. Creating the RX-only Design x
1.5.1. Generating the Design 1.5.2. Removing Irrelevant Blocks 1.5.3. Making a Direct Connection to the RX Transceiver Block 1.5.4. Selecting the Bitec FMC Daughter Card Revision 1.5.5. Modifying the Software
1.5.2. Removing Irrelevant Blocks x
1.5.2.1. Removing Irrelevant Block in Top Level Example Design a10_dp_demo.v File 1.5.2.2. Removing Irrelevant Block in Platform Designer
1. Intel® Arria® 10 DisplayPort 8K RX-only Design

1.4.4. Running the Design on Hardware

Set up the hardware before you run the design on the Intel® Arria® 10 development kit.
Figure 2.  Intel® Arria® 10 Development Kit Setup
  1. Install the Bitec FMC daughter card at the FMC port A on the Intel® Arria® 10 development kit.
  2. Connect the DisplayPort RX connector on the Bitec FMC daughter card to a video source such as GPU.
  3. Ensure all MSEL switches on the development board are in default position.
  4. Power up and connect the development board to your PC using a micro USB cable.
  5. Download the .sof file into the FPGA device using Intel® Quartus® Prime Programmer.
    Note: If you regenerate the .elf file without recompiling the Intel® Quartus® Prime project, you need to download the .elf file after download the .sof file. The reference design contains a pre-compiled the .sof file that you can use to program the Intel® Arria® 10 development kit. You need to unzip the Additional_Files.zip and locate the a10_dp_demo.sof in the Master_Image/Rev11 directory.
  6. Push the Reset button on the Intel® Arria® 10 development kit.
  7. Run the command below in the Nios® II Command Shell to interface with in-design Nios® II core. 
    nios2-terminal
  8. To view the MSA information, type ‘S’ on the keyboard while in the Nios® II terminal. You can also view the MSA information by pressing the push button 0 on the Intel® Arria® 10 development kit.
    Other available commands:
    • h - help
    • s - MSA status
    • c - Read Sink DPCD CRC
    • v - Print versions
    Figure 3. DisplayPort RX-only Design MSA InformationThe MSA information tells you that the DisplayPort RX has successfully received the video data without any bit error rate (BER). The MSA information also tells you that the DisplayPort RX receives 7680x4320 video resolution using 4 channels, 8100 Mbps (HBR3) per channel with 8 bpc RGB colorimetry (MISC0 = 20). MSA lock = 1 indicates that the video stream received by the sink is a valid video stream.
Figure 4. Sink Device Detected by the GPU Control PanelThis design used the Nvidia GeForce GTX 1080 GPU for verification. This figure below is a screen-shot of the Nvidia GPU control panel environment.
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