AN 900: Intel® Arria 10 DisplayPort 8K RX-only Design

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ID 683799
Date 7/02/2021
Public
Document Table of Contents
Document Table of Contents x
1. Intel® Arria® 10 DisplayPort 8K RX-only Design
1. Intel® Arria® 10 DisplayPort 8K RX-only Design x
1.1. Design Components 1.2. Clocking Scheme 1.3. Top Level Interface Signals 1.4. Quick Start Guide 1.5. Creating the RX-only Design 1.6. Document Revision History for AN 900: Intel® Arria® 10 DisplayPort 8K RX-only Design
1.4. Quick Start Guide x
1.4.1. Hardware and Software Requirements 1.4.2. Directory Structure 1.4.3. Compiling the Design 1.4.4. Running the Design on Hardware 1.4.5. Design Debug Features
1.4.3. Compiling the Design x
1.4.3.1. Regenerating and Downloading ELF File
1.4.5. Design Debug Features x
1.4.5.1. Main Stream Attribute (MSA) Information 1.4.5.2. Auxiliary Channel Traffic Monitor 1.4.5.3. Signal Tap Logic Analyzer 1.4.5.4. Onboard User LED Functions
1.5. Creating the RX-only Design x
1.5.1. Generating the Design 1.5.2. Removing Irrelevant Blocks 1.5.3. Making a Direct Connection to the RX Transceiver Block 1.5.4. Selecting the Bitec FMC Daughter Card Revision 1.5.5. Modifying the Software
1.5.2. Removing Irrelevant Blocks x
1.5.2.1. Removing Irrelevant Block in Top Level Example Design a10_dp_demo.v File 1.5.2.2. Removing Irrelevant Block in Platform Designer
1. Intel® Arria® 10 DisplayPort 8K RX-only Design

1.5.5. Modifying the Software

After removing the irrelevant blocks, reconnecting the remaining blocks, and selecting the Bitec FMC daughter card revision, modify the software.
  1. First, modify the software's config.h file. Navigate to the design example folder and change the values of the following parameter settings in the file.
    Table 13.  Config.h Parameter Settings
    Parameter Value Description
    BITEC_AUX_DEBUG 0 Set to 1 to enable AUX channel traffic monitoring.
    BITEC_STATUS_DEBUG 1 Set to 1 to enable MSA and link status monitoring.
    DP_SUPPORT_RX 1 Set to 1 if the DisplayPort supports RX.
    BITEC_RX_GPUMODE 1 Set to 1 to enable sink GPU mode.
    BITEC_RX_CAPAB_MST 0 Set to 1 to enable MST support.
    BITEC_RX_FAST_LT_SUPPORT 0 Set to 1 to enable Fast Link Training support.
    BITEC_RX_LQA_SUPPORT 0 Set to 1 to enable Link Quality Analysis support.
    BITEC_EDID_800X600_AUDIO 0 Set to 1 to use an EDID with maximum resolution of 800 x 600
    BITEC_DP_0_AV_RX_CONTROL_BITEC_CFG_RX_SUPPORT_MST 0 Set to 1 to enable MST support
    DP_SUPPORT_TX 0 Set to 1 if DisplayPort supports TX
    BITEC_TX_CAPAB_MST 0 Set to 1 to enable MST support
    TX_VIDEO_IM_ENABLE 0 Set to 1 to enable TX Video IM interface
    DP_SUPPORT_EDID_PASSTHRU 0 Set to 1 to enable EDID passthrough from sink to source.
    BITEC_DP_CARD_REV 0, 1 or 2
    • Set to 0 = Bitec FMC DisplayPort daughter card revision 4 – 8 (without Paradetech Retimer)
    • Set to 1 = Bitec FMC DisplayPort daughter card revision 9 and 10 (with Paradetech Retimer)
    • Set to 2 = Bitec FMC DisplayPort daughter card revision 11 (with Megachip Retimer)
    MST_RX_STREAMS 0 RX MST number of streams
    MST_TX_STREAMS 0 TX MST number of streams
    PSG_8K_EDID 1 Set to 1 is sink supports 8K video.
  2. Next, open the main.c file located in the software/dp_demo folder, and remove any TX-related components, such as the following:

    - #include “tx_utils.h”

    - bitec_dptx_init();

    - bitec_dp_dump_source_msa(btc_dptx_baseaddr(0));

    - bitec_dp_dump_source_config(btc_dptx_baseaddr(0));

    Note: Remove the tx_utils.c and tx_utils.h files from the software folder to avoid potential software build errors.
  3. Next, for debugging purposes, modify the debug.c file located in the software/dp_demo folder. Open the debug.c file and remove the void bitec_dp_dump_source_msa() and void bitec_dp_dump_source_config() functions.
  4. After modifying the software, rebuild the software as instructed in Regenerating and Downloading ELF File.
  5. Finally, compile the project as described in Compiling the Design.
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