AN 900: Intel® Arria 10 DisplayPort 8K RX-only Design

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ID 683799
Date 7/02/2021
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Document Table of Contents
Document Table of Contents x
1. Intel® Arria® 10 DisplayPort 8K RX-only Design
1. Intel® Arria® 10 DisplayPort 8K RX-only Design x
1.1. Design Components 1.2. Clocking Scheme 1.3. Top Level Interface Signals 1.4. Quick Start Guide 1.5. Creating the RX-only Design 1.6. Document Revision History for AN 900: Intel® Arria® 10 DisplayPort 8K RX-only Design
1.4. Quick Start Guide x
1.4.1. Hardware and Software Requirements 1.4.2. Directory Structure 1.4.3. Compiling the Design 1.4.4. Running the Design on Hardware 1.4.5. Design Debug Features
1.4.3. Compiling the Design x
1.4.3.1. Regenerating and Downloading ELF File
1.4.5. Design Debug Features x
1.4.5.1. Main Stream Attribute (MSA) Information 1.4.5.2. Auxiliary Channel Traffic Monitor 1.4.5.3. Signal Tap Logic Analyzer 1.4.5.4. Onboard User LED Functions
1.5. Creating the RX-only Design x
1.5.1. Generating the Design 1.5.2. Removing Irrelevant Blocks 1.5.3. Making a Direct Connection to the RX Transceiver Block 1.5.4. Selecting the Bitec FMC Daughter Card Revision 1.5.5. Modifying the Software
1.5.2. Removing Irrelevant Blocks x
1.5.2.1. Removing Irrelevant Block in Top Level Example Design a10_dp_demo.v File 1.5.2.2. Removing Irrelevant Block in Platform Designer
1. Intel® Arria® 10 DisplayPort 8K RX-only Design

1.1. Design Components

The DisplayPort Intel® FPGA IP design example requires these components.
Table 1.  Core System Components
Module Description
Core System (Platform Designer)

The core system consists of the Nios® II processor and its necessary components, and the DisplayPort RX core sub-systems.

This system provides the infrastructure to interconnect the Nios® II processor with the DisplayPort Intel® FPGA IP (RX instance) through Avalon® memory-mapped interface within a single Platform Designer system to ease the software build flow.

This system consists of:
  • CPU Sub-system
  • RX Sub-system
RX Sub-system (Platform Designer)
The RX sub-system consists of:
  • Clock Source—The clock source to the DisplayPort RX core. This sub-system has two clock integrated sources: 300 MHz and 16 MHz.
  • Reset Bridge—The bridge that connects the external signal to the sub-system. This bridge synchronizes to a respective clock source before it is used.
  • DisplayPort RX core—DisplayPort sink core, VESA DisplayPort Standard version 1.4.
  • Debug FIFO—This FIFO captures all DisplayPort RX auxiliary cycles, and prints out in the Nios® II Debug terminal.
  • PIO—The parallel IO that triggers the Main Stream Attribute (MSA) captured and prints out when you press the onboard push button..
  • Avalon® Memory-Mapped Pipeline Bridge—This bridge interconnects the Avalon® memory-mapped interface between components within the RX sub-system to the Nios® II processor in the Core sub-system.
  • EDID—The EDID RAM stores the desired EDID values in the RAM and connects to DisplayPort sink core. The design uses this component only when you turn off the Enable GPU Control option in the RX core.
Table 2.  DisplayPort RX PHY Top Components
Module Description
RX PHY Top
The RX PHY top level consists of the components related to the receiver PHY layer.
  • Transceiver Native PHY(RX)—The hard transceiver block that receives the serial data from an external video and deserializes it to 20-bit or 40-bit parallel data for the DisplayPort Intel® FPGA IP sink core.
  • Transceiver PHY Reset Controller—The RX Reconfiguration Management module triggers the reset input of this controller to generate the corresponding analog and digital reset signals to the Transceiver Native PHY block according to the reset sequencing.
  • RX Reconfiguration Management—This block reconfigures and recalibrates the Transceiver Native PHY to receive serial data in the supported data rates (RBR, HBR, HBR2, and HBR3).
Note: 8.1 Gbps is available only in the Intel® Quartus® Prime Pro Edition software.
Table 3.  Top-Level Common Block
Module Description
Video PLL

IOPLL generates two common source clocks:

  • 300 MHz—Used as DisplayPort RX sink video clock source.
  • 16 MHz—Used as DisplayPort RX auxiliary clock.
Level Two Title