AN 900: Intel® Arria 10 DisplayPort 8K RX-only Design

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ID 683799
Date 7/02/2021
Public
Document Table of Contents
Document Table of Contents x
1. Intel® Arria® 10 DisplayPort 8K RX-only Design
1. Intel® Arria® 10 DisplayPort 8K RX-only Design x
1.1. Design Components 1.2. Clocking Scheme 1.3. Top Level Interface Signals 1.4. Quick Start Guide 1.5. Creating the RX-only Design 1.6. Document Revision History for AN 900: Intel® Arria® 10 DisplayPort 8K RX-only Design
1.4. Quick Start Guide x
1.4.1. Hardware and Software Requirements 1.4.2. Directory Structure 1.4.3. Compiling the Design 1.4.4. Running the Design on Hardware 1.4.5. Design Debug Features
1.4.3. Compiling the Design x
1.4.3.1. Regenerating and Downloading ELF File
1.4.5. Design Debug Features x
1.4.5.1. Main Stream Attribute (MSA) Information 1.4.5.2. Auxiliary Channel Traffic Monitor 1.4.5.3. Signal Tap Logic Analyzer 1.4.5.4. Onboard User LED Functions
1.5. Creating the RX-only Design x
1.5.1. Generating the Design 1.5.2. Removing Irrelevant Blocks 1.5.3. Making a Direct Connection to the RX Transceiver Block 1.5.4. Selecting the Bitec FMC Daughter Card Revision 1.5.5. Modifying the Software
1.5.2. Removing Irrelevant Blocks x
1.5.2.1. Removing Irrelevant Block in Top Level Example Design a10_dp_demo.v File 1.5.2.2. Removing Irrelevant Block in Platform Designer
1. Intel® Arria® 10 DisplayPort 8K RX-only Design

1.5.3. Making a Direct Connection to the RX Transceiver Block

The existing dynamic DisplayPort parallel SST loopback with PCR design example uses the Transceiver Arbiter block to share between an RX and TX Native PHY transceiver within the same channel. As the RX-only design only requires the RX transceiver, you need to remove the Transceiver Arbiter and make a direct connection to the RX transceiver.
  1. Before you make the connection, in the Platform Designer turn on the Share Reconfiguration Interface parameter in the Transceiver Native PHY block to allow for single Avalon® memory-mapped slave interface for dynamic reconfiguration of all channels.
  2. Update the width of the transceiver signals as shown below in the design top-level and the rx_phy_top.v files.
    Table 12.  RX Transceiver Signals
    Signal Direction Width (Bit)
    gxb_rx_rcfg_write Input 1
    gxb_rx_rcfg_read Input 1
    gxb_rx_rcfg_address Input 12
    gxb_rx_rcfg_writedata Input 32
    gxb_rx_rcfg_readdata Output 32
    gxb_rx_rcfg_waitrequest Output 1
    gxb_rx_rcfg_cal_busy Output 1
  3. Make a direct connection from the RX Reconfiguration Management block to the RX Transceiver Native PHY block in the rx_phy_top.v file as shown in the diagram below.
    Figure 7. Bitec Reconfig and RX Transceiver Block Connection
  4. Remove the following Transceiver Reconfig Group assignments from the Intel® Quartus® Prime Settings File (.qsf).
    • - set_instance_assignment -name XCVR_RECONFIG_GROUP 1 -to fmca_dp_m2c_p[0] -entity a10_dp_demo
    • - set_instance_assignment -name XCVR_RECONFIG_GROUP 2 -to fmca_dp_m2c_p[1] -entity a10_dp_demo
    • - set_instance_assignment -name XCVR_RECONFIG_GROUP 3 -to fmca_dp_m2c_p[2] -entity a10_dp_demo
    • - set_instance_assignment -name XCVR_RECONFIG_GROUP 4 -to fmca_dp_m2c_p[3] -entity a10_dp_demo
Level Two Title