AN 900: Intel® Arria 10 DisplayPort 8K RX-only Design

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ID 683799
Date 7/02/2021
Public
Document Table of Contents
Document Table of Contents x
1. Intel® Arria® 10 DisplayPort 8K RX-only Design
1. Intel® Arria® 10 DisplayPort 8K RX-only Design x
1.1. Design Components 1.2. Clocking Scheme 1.3. Top Level Interface Signals 1.4. Quick Start Guide 1.5. Creating the RX-only Design 1.6. Document Revision History for AN 900: Intel® Arria® 10 DisplayPort 8K RX-only Design
1.4. Quick Start Guide x
1.4.1. Hardware and Software Requirements 1.4.2. Directory Structure 1.4.3. Compiling the Design 1.4.4. Running the Design on Hardware 1.4.5. Design Debug Features
1.4.3. Compiling the Design x
1.4.3.1. Regenerating and Downloading ELF File
1.4.5. Design Debug Features x
1.4.5.1. Main Stream Attribute (MSA) Information 1.4.5.2. Auxiliary Channel Traffic Monitor 1.4.5.3. Signal Tap Logic Analyzer 1.4.5.4. Onboard User LED Functions
1.5. Creating the RX-only Design x
1.5.1. Generating the Design 1.5.2. Removing Irrelevant Blocks 1.5.3. Making a Direct Connection to the RX Transceiver Block 1.5.4. Selecting the Bitec FMC Daughter Card Revision 1.5.5. Modifying the Software
1.5.2. Removing Irrelevant Blocks x
1.5.2.1. Removing Irrelevant Block in Top Level Example Design a10_dp_demo.v File 1.5.2.2. Removing Irrelevant Block in Platform Designer
1. Intel® Arria® 10 DisplayPort 8K RX-only Design

1.6. Document Revision History for AN 900: Intel® Arria® 10 DisplayPort 8K RX-only Design

Document Version Changes
2021.07.02
  • Added Bitec FMC daughter card revision 8 to Hardware and Software Requirements.
  • Added the step to extract the file inCompiling the Design.
  • Edited the step in Regenerating and Downloading ELF File.
  • Pointed Reset Button in Figure: Intel Arria 10 Development Kit Setup.
  • Changed from output to input in Design Debug Features.
  • Added the steps in Creating the RX-only Design.
  • Added subtopic Removing Irrelevant Block in Top Level Example Design a10_dp_demo.v File and Removing Irrelevant Block in Platform Designer in section Removing Irrelevant Blocks.
  • Edited the steps and changed the Figure:Bitec Reconfig and RX Transceiver Block Connection in Making a Direct Connection to the RX Transceiver Block.
2019.12.16 Initial release.
Level Two Title