Intel® MAX® 10 FPGA Device Datasheet

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ID 683794
Date 10/31/2022
Public
Document Table of Contents
Document Table of Contents x
Intel® MAX® 10 FPGA Device Datasheet
Intel® MAX® 10 FPGA Device Datasheet x
Electrical Characteristics Switching Characteristics Configuration Specifications I/O Timing Programmable IOE Delay Glossary Document Revision History for the Intel® MAX® 10 FPGA Device Datasheet
Electrical Characteristics x
Operating Conditions
Operating Conditions x
Absolute Maximum Ratings Maximum Allowed Overshoot During Transitions over a 11.4-Year Time Frame Recommended Operating Conditions Programming/Erasure Specifications DC Characteristics I/O Standards Specifications
Absolute Maximum Ratings x
Single Supply Devices Absolute Maximum Ratings Dual Supply Devices Absolute Maximum Ratings Absolute Maximum Ratings
Recommended Operating Conditions x
Single Supply Devices Power Supplies Recommended Operating Conditions Dual Supply Devices Power Supplies Recommended Operating Conditions Recommended Operating Conditions
DC Characteristics x
Supply Current and Power Consumption I/O Pin Leakage Current Bus Hold Parameters Series OCT without Calibration Specifications Series OCT with Calibration at Device Power-Up Specifications OCT Variation after Calibration at Device Power-Up Pin Capacitance Internal Weak Pull-Up Resistor Hot-Socketing Specifications Hysteresis Specifications for Schmitt Trigger Input
I/O Standards Specifications x
Single-Ended I/O Standards Specifications Single-Ended SSTL, HSTL, and HSUL I/O Reference Voltage Specifications Single-Ended SSTL, HSTL, and HSUL I/O Standards Signal Specifications Differential SSTL I/O Standards Specifications Differential HSTL and HSUL I/O Standards Specifications Differential I/O Standards Specifications
Switching Characteristics x
Core Performance Specifications Periphery Performance Specifications
Core Performance Specifications x
Clock Tree Specifications PLL Specifications Embedded Multiplier Specifications Memory Block Performance Specifications Internal Oscillator Specifications UFM Performance Specifications ADC Performance Specifications
ADC Performance Specifications x
Single Supply Devices ADC Performance Specifications Dual Supply Devices ADC Performance Specifications
Periphery Performance Specifications x
High-Speed I/O Specifications Memory Standards Supported by the Soft Memory Controller Memory Output Clock Jitter Specifications
High-Speed I/O Specifications x
True PPDS and Emulated PPDS_E_3R Transmitter Timing Specifications True RSDS and Emulated RSDS_E_3R Transmitter Timing Specifications Emulated RSDS_E_1R Transmitter Timing Specifications True Mini-LVDS and Emulated Mini-LVDS_E_3R Transmitter Timing Specifications True LVDS Transmitter Timing Emulated LVDS_E_3R, SLVS, and Sub-LVDS Transmitter Timing Specifications LVDS, TMDS, HiSpi, SLVS, and Sub-LVDS Receiver Timing Specifications
Configuration Specifications x
JTAG Timing Parameters Remote System Upgrade Circuitry Timing Specifications User Watchdog Internal Circuitry Timing Specifications Uncompressed Raw Binary File (.rbf) Sizes Internal Configuration Time Internal Configuration Timing Parameter
Programmable IOE Delay x
Programmable IOE Delay On Row Pins Programmable IOE Delay for Column Pins
Intel® MAX® 10 FPGA Device Datasheet

True Mini-LVDS and Emulated Mini-LVDS_E_3R Transmitter Timing Specifications

Table 40.  True Mini-LVDS and Emulated Mini-LVDS_E_3R Transmitter Timing Specifications for Intel® MAX® 10 Dual Supply Devices True mini-LVDS transmitter is only supported at the bottom I/O banks. Emulated mini-LVDS_E_3R transmitter is supported at the output pin of all I/O banks.
Symbol Parameter Mode –I6, –A6, –C7, –I7 –A7 –C8, –I8 Unit
Min Typ Max Min Typ Max Min Typ Max
fHSCLK Input clock frequency (high-speed I/O performance pin) ×10 5 — 155 5 — 155 5 — 155 MHz
×8 5 — 155 5 — 155 5 — 155 MHz
×7 5 — 155 5 — 155 5 — 155 MHz
×4 5 — 155 5 — 155 5 — 155 MHz
×2 5 — 155 5 — 155 5 — 155 MHz
×1 5 — 310 5 — 310 5 — 310 MHz
HSIODR Data rate (high-speed I/O performance pin) ×10 100 — 310 100 — 310 100 — 310 Mbps
×8 80 — 310 80 — 310 80 — 310 Mbps
×7 70 — 310 70 — 310 70 — 310 Mbps
×4 40 — 310 40 — 310 40 — 310 Mbps
×2 20 — 310 20 — 310 20 — 310 Mbps
×1 10 — 310 10 — 310 10 — 310 Mbps
fHSCLK Input clock frequency (low-speed I/O performance pin) ×10 5 — 150 5 — 150 5 — 150 MHz
×8 5 — 150 5 — 150 5 — 150 MHz
×7 5 — 150 5 — 150 5 — 150 MHz
×4 5 — 150 5 — 150 5 — 150 MHz
×2 5 — 150 5 — 150 5 — 150 MHz
×1 5 — 300 5 — 300 5 — 300 MHz
HSIODR Data rate (low-speed I/O performance pin) ×10 100 — 300 100 — 300 100 — 300 Mbps
×8 80 — 300 80 — 300 80 — 300 Mbps
×7 70 — 300 70 — 300 70 — 300 Mbps
×4 40 — 300 40 — 300 40 — 300 Mbps
×2 20 — 300 20 — 300 20 — 300 Mbps
×1 10 — 300 10 — 300 10 — 300 Mbps
tDUTY Duty cycle on transmitter output clock — 45 — 55 45 — 55 45 — 55 %
TCCS63 Transmitter channel-to-channel skew — — — 300 — — 300 — — 300 ps
tx Jitter 64 Output jitter (high-speed I/O performance pin) — — — 425 — — 425 — — 425 ps
Output jitter (low-speed I/O performance pin) — — — 470 — — 470 — — 470 ps
tRISE Rise time 20 – 80%, CLOAD = 5 pF — 500 — — 500 — — 500 — ps
tFALL Fall time 20 – 80%, CLOAD = 5 pF — 500 — — 500 — — 500 — ps
tLOCK Time required for the PLL to lock, after CONF_DONE signal goes high, indicating the completion of device configuration — — — 1 — — 1 — — 1 ms
63 TCCS specifications apply to I/O banks from the same side only.
64 TX jitter is the jitter induced from core noise and I/O switching noise.
Level Two Title