Intel® MAX® 10 FPGA Device Datasheet

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ID 683794
Date 10/31/2022
Public
Document Table of Contents
Document Table of Contents x
Intel® MAX® 10 FPGA Device Datasheet
Intel® MAX® 10 FPGA Device Datasheet x
Electrical Characteristics Switching Characteristics Configuration Specifications I/O Timing Programmable IOE Delay Glossary Document Revision History for the Intel® MAX® 10 FPGA Device Datasheet
Electrical Characteristics x
Operating Conditions
Operating Conditions x
Absolute Maximum Ratings Maximum Allowed Overshoot During Transitions over a 11.4-Year Time Frame Recommended Operating Conditions Programming/Erasure Specifications DC Characteristics I/O Standards Specifications
Absolute Maximum Ratings x
Single Supply Devices Absolute Maximum Ratings Dual Supply Devices Absolute Maximum Ratings Absolute Maximum Ratings
Recommended Operating Conditions x
Single Supply Devices Power Supplies Recommended Operating Conditions Dual Supply Devices Power Supplies Recommended Operating Conditions Recommended Operating Conditions
DC Characteristics x
Supply Current and Power Consumption I/O Pin Leakage Current Bus Hold Parameters Series OCT without Calibration Specifications Series OCT with Calibration at Device Power-Up Specifications OCT Variation after Calibration at Device Power-Up Pin Capacitance Internal Weak Pull-Up Resistor Hot-Socketing Specifications Hysteresis Specifications for Schmitt Trigger Input
I/O Standards Specifications x
Single-Ended I/O Standards Specifications Single-Ended SSTL, HSTL, and HSUL I/O Reference Voltage Specifications Single-Ended SSTL, HSTL, and HSUL I/O Standards Signal Specifications Differential SSTL I/O Standards Specifications Differential HSTL and HSUL I/O Standards Specifications Differential I/O Standards Specifications
Switching Characteristics x
Core Performance Specifications Periphery Performance Specifications
Core Performance Specifications x
Clock Tree Specifications PLL Specifications Embedded Multiplier Specifications Memory Block Performance Specifications Internal Oscillator Specifications UFM Performance Specifications ADC Performance Specifications
ADC Performance Specifications x
Single Supply Devices ADC Performance Specifications Dual Supply Devices ADC Performance Specifications
Periphery Performance Specifications x
High-Speed I/O Specifications Memory Standards Supported by the Soft Memory Controller Memory Output Clock Jitter Specifications
High-Speed I/O Specifications x
True PPDS and Emulated PPDS_E_3R Transmitter Timing Specifications True RSDS and Emulated RSDS_E_3R Transmitter Timing Specifications Emulated RSDS_E_1R Transmitter Timing Specifications True Mini-LVDS and Emulated Mini-LVDS_E_3R Transmitter Timing Specifications True LVDS Transmitter Timing Emulated LVDS_E_3R, SLVS, and Sub-LVDS Transmitter Timing Specifications LVDS, TMDS, HiSpi, SLVS, and Sub-LVDS Receiver Timing Specifications
Configuration Specifications x
JTAG Timing Parameters Remote System Upgrade Circuitry Timing Specifications User Watchdog Internal Circuitry Timing Specifications Uncompressed Raw Binary File (.rbf) Sizes Internal Configuration Time Internal Configuration Timing Parameter
Programmable IOE Delay x
Programmable IOE Delay On Row Pins Programmable IOE Delay for Column Pins
Intel® MAX® 10 FPGA Device Datasheet

Memory Output Clock Jitter Specifications

Intel® MAX® 10 devices support external memory interfaces up to 303 MHz. The external memory interfaces for Intel® MAX® 10 devices calibrate automatically.

The memory output clock jitter measurements are for 200 consecutive clock cycles.

The clock jitter specification applies to memory output clock pins generated using DDIO circuits clocked by a PLL output routed on a PHY clock network.

DDR3 and LPDDR2 SDRAM memory interfaces are only supported on the fast speed grade device.

Table 50.  Memory Output Clock Jitter Specifications for Intel® MAX® 10 Devices
Parameter Symbol –6 Speed Grade –7 Speed Grade Unit
Min Max Min Max
Clock period jitter tJIT(per) –127 127 –215 215 ps
Cycle-to-cycle period jitter tJIT(cc) — 242 — 360 ps
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