Document Revision History for the Intel® MAX® 10 FPGA Device Datasheet

Intel® MAX® 10 FPGA Device Datasheet

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ID 683794

Date 10/31/2022

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Document Revision History for the Intel® MAX® 10 FPGA Device Datasheet

Document Version	Changes
2022.10.31	Added support for –I8 speed grade. Updated footnote to 1.0 V LVCMOS I/O standard in the Single-Ended I/O Standards Specifications table. Added specifications for 1.8 V LVDS I/O standard in the Differential I/O Standards Specifications for Intel® MAX® 10 Devices table. Added the following tables: True 1.8 V LVDS Transmitter Timing Specifications for Intel® MAX® 10 Dual Supply Devices True 1.8 V LVDS Receiver Timing Specifications for Intel® MAX® 10 Dual Supply Devices Updated the Memory Standards Supported by the Soft Memory Controller for Intel® MAX® 10 Devices table. Removed contact information for –A6 speed grade devices. Added note on automotive-grade devices do not support external memory interfaces.
2021.11.01	Updated footnote for 1.0 V LVCMOS to include new devices in the Single-Ended I/O Standards Specifications for Intel® MAX® 10 Devices table. Removed –I6 speed grade from contact information in the following tables. All OPNs for –I6 speed grade are available in the Intel® Quartus® Prime Standard Edition software version 21.1 onwards. Intel® MAX® 10 Device Grades and Speed Grades Supported Memory Standards Supported by the Soft Memory Controller for Intel® MAX® 10 Devices
2020.06.30	Added V_CCIO specifications for 1.0 V in the following tables: Power Supplies Recommended Operating Conditions for Intel® MAX® 10 Single Supply Devices Power Supplies Recommended Operating Conditions for Intel® MAX® 10 Dual Supply Devices Added 1.0 V LVCMOS specifications in the Single-Ended I/O Standards Specifications for Intel® MAX® 10 Devices table. Added specifications for 10M02SCU324 device in the following tables: Uncompressed .rbf Sizes for Intel® MAX® 10 Devices Internal Configuration Time for Intel® MAX® 10 Devices (Uncompressed .rbf) Internal Configuration Time for Intel® MAX® 10 Devices (Compressed .rbf)
2018.06.29	Removed links on instant-on feature. Added JTAG timing specifications term in Glossary. Renamed the following IP cores as per Intel rebranding: Renamed Altera Modular ADC IP core to Modular ADC core Intel FPGA IP core. Renamed Altera Modular Dual ADC IP core to Modular Dual ADC core Intel FPGA IP core.

Date	Version	Changes
December 2017	2017.12.15	Removed the units for "Input resistance" and "Input capacitance" parameters in the following tables: ADC Performance Specifications for Intel® MAX® 10 Single Supply Devices ADC Performance Specifications for Intel® MAX® 10 Dual Supply Devices Removed the specification with memory initialization for 10M02 device in the Uncompressed .rbf Sizes for Intel® MAX® 10 Devices table.
June 2017	2017.06.16	Added notes for T_J for Industrial and Automotive devices in Recommended Operating Conditions for Intel® MAX® 10 Devices table. Updated the parameter in Internal Weak Pull-Up Resistor for Intel® MAX® 10 Devices table. Changed "Performance" to "Frequency" in UFM Performance Specifications for Intel® MAX® 10 Devices table. Removed PowerPlay text from tool name.
February 2017	2017.02.21	Rebranded as Intel.
October 2016	2016.10.31	Updated the note to the Intel® MAX® 10 Device Grades and Speed Grades Supported table. Updated the Memory Standards Supported by the Soft Memory Controller for Intel® MAX® 10 Devices table.
May 2016	2016.05.02	Updated t_RAMP specifications in Recommended Operating Conditions for Intel® MAX® 10 Devices table. Removed standard POR and fast POR specifications. Updated maximum value from 3 ms to 10 ms and added a not for the minimum value. Added Supply Current and Power Consumption section. Added the following tables: Memory Standards Supported by the Soft Memory Controller for Intel® MAX® 10 Devices Internal Configuration Timing Parameter for Intel® MAX® 10 Devices Removed POR Delay Specifications for Intel® MAX® 10 Devices table. Updated the description in the Internal Configuration Time section. Updated the following tables: Internal Configuration Time for Intel® MAX® 10 Devices (Uncompressed .rbf) Internal Configuration Time for Intel® MAX® 10 Devices (Compressed .rbf)
January 2016	2016.01.22	Added description about automotive temperature devices in the Programming/Erasure Specifications table. Changed the pin capacitance to maximum values. Updated maximum TCCS specifications from 410 ps to 300 ps in the following tables: True PPDS and Emulated PPDS_E_3R Transmitter Timing Specifications for Intel® MAX® 10 Dual Supply Devices True RSDS and Emulated RSDS_E_3R Transmitter Timing Specifications for Intel® MAX® 10 Dual Supply Devices Emulated RSDS_E_1R Transmitter Timing Specifications for Intel® MAX® 10 Dual Supply Devices True Mini-LVDS and Emulated Mini-LVDS_E_3R Transmitter Timing Specifications for Intel® MAX® 10 Dual Supply Devices True LVDS Transmitter Timing Specifications for Intel® MAX® 10 Single Supply Devices True LVDS Transmitter Timing Specifications for Intel® MAX® 10 Dual Supply Devices Emulated LVDS_E_3R Transmitter Timing Specifications for Intel® MAX® 10 Single Supply Devices Emulated LVDS_E_3R, SLVS, and Sub-LVDS Transmitter Timing Specifications for Intel® MAX® 10 Dual Supply Devices Added new table: True RSDS and Emulated RSDS_E_3R Transmitter Timing Specifications for Intel® MAX® 10 Single Supply Devices. Updated maximum f_HSCLK and HSIODR specifications for –A6, –C7, and –I7 speed grades in True LVDS Transmitter Timing Specifications for Intel® MAX® 10 Dual Supply Devices table. Updated SW specifications in the following tables: LVDS Receiver Timing Specifications for Intel® MAX® 10 Single Supply Devices LVDS, TMDS, HiSpi, SLVS, and Sub-LVDS Receiver Timing Specifications for Intel® MAX® 10 Dual Supply Devices Updated maximum f_HSCLK and HSIODR (high-speed I/O performance pin) specifications for –I6, –A6, –C7, –I7 speed grades in LVDS, TMDS, HiSpi, SLVS, and Sub-LVDS Receiver Timing Specifications for Intel® MAX® 10 Dual Supply Devices table. Removed Internal Configuration Time information in the Uncompressed .rbf Sizes for Intel® MAX® 10 Devices table. Added Internal Configuration Time tables for uncompressed .rbf files and compressed .rbf files. Removed Preliminary tags for all tables.
November 2015	2015.11.02	Added description to Maximum Allowed Overshoot During Transitions over a 11.4-Year Time Frame topic. Added `ADC_VREF` Pin Leakage Current for Intel® MAX® 10 Devices table. Updated the condition for "Bus-hold high, sustaining current" parameter from "V_IN < V_IL (minimum)" to "V_IN < V_IH (minimum)" in Bus Hold Parameters table. Added –A6 speed grade in the following tables: Intel® MAX® 10 Device Grades and Speed Grades Supported Series OCT without Calibration Specifications for Intel® MAX® 10 Devices Clock Tree Specifications for Intel® MAX® 10 Devices Embedded Multiplier Specifications for Intel® MAX® 10 Devices Memory Block Performance Specifications for Intel® MAX® 10 Devices True PPDS and Emulated PPDS_E_3R Transmitter Timing Specifications for Intel® MAX® 10 Dual Supply Devices True RSDS and Emulated RSDS_E_3R Transmitter Timing Specifications for Intel® MAX® 10 Dual Supply Devices Emulated RSDS_E_1R Transmitter Timing Specifications for Intel® MAX® 10 Dual Supply Devices True Mini-LVDS and Emulated Mini-LVDS_E_3R Transmitter Timing Specifications for Intel® MAX® 10 Dual Supply Devices True LVDS Transmitter Timing Specifications for Intel® MAX® 10 Dual Supply Devices Emulated LVDS_E_3R, SLVS, and Sub-LVDS Transmitter Timing Specifications for Intel® MAX® 10 Dual Supply Devices LVDS, TMDS, HiSpi, SLVS, and Sub-LVDS Receiver Timing Specifications for Intel® MAX® 10 Dual Supply Devices IOE Programmable Delay on Row Pins for Intel® MAX® 10 Devices IOE Programmable Delay on Column Pins for Intel® MAX® 10 Devices Updated the maximum value for input clock cycle-to-cycle jitter (t_{INJITTER_CCJ}) with F_INPFD < 100 MHz condition from 750 ps to ±750 ps in PLL Specifications for Intel® MAX® 10 Devices table. Updated the dual supply mode performance in Embedded Multiplier Specifications for Intel® MAX® 10 Devices table. Updated the dual supply mode performance in Memory Block Performance Specifications for Intel® MAX® 10 Devices table. Added typical specifications in Internal Oscillator Frequencies for Intel® MAX® 10 Devices table. Updated specifications in UFM Performance Specifications for Intel® MAX® 10 Devices table. Updated sampling window specifications in LVDS, TMDS, HiSpi, SLVS, and Sub-LVDS Receiver Timing Specifications for Intel® MAX® 10 Dual Supply Devices table. Updated IOE programmable delay for row and column pins. Changed instances of Quartus II to Quartus Prime.
June 2015	2015.06.12	Updated the maximum values in Internal Weak Pull-Up Resistor for Intel® MAX® 10 Devices table. Removed Internal Weak Pull-Up Resistor equation. Updated the note for input resistance and input capacitance parameters in the ADC Performance Specifications table for both single supply and dual supply devices. Note: Download the SPICE models for simulation. Added a note to AC Accuracy - THD, SNR, and SINAD parameters in the ADC Performance Specifications for Intel® MAX® 10 Dual Supply Devices table. Note: When using internal V_REF, THD = 66 dB, SNR = 58 dB and SINAD = 57.5 dB for dedicated ADC input channels. Updated clock period jitter and cycle-to-cycle period jitter parameters in the Memory Output Clock Jitter Specifications for Intel® MAX® 10 Devices table.
May 2015	2015.05.04	Updated a note to V_CCIO for both single supply and dual supply power supplies recommended operating conditions tables. Note updated: V_CCIO for all I/O banks must be powered up during user mode because V_CCIO I/O banks are used for the ADC and I/O functionalities. Updated Example for OCT Resistance Calculation after Calibration at Device Power-Up. Removed a note to BLVDS in Differential I/O Standards Specifications for Intel® MAX® 10 Devices table. BLVDS is now supported in Intel® MAX® 10 single supply devices. Note removed: BLVDS TX is not supported in single supply devices. Updated ADC Performance Specifications for both single supply and dual supply devices. Changed the symbol for Operating junction temperature range parameter from T_A to T_J. Edited sampling rate maximum value from 1000 kSPS to 1 MSPS. Added a note to analog input voltage parameter. Removed input frequency, f_IN specification. Updated the condition for DNL specification: External V_REF, no missing code. Added DNL specification for condition: Internal V_REF, no missing code. Added notes to AC accuracy specifications that the value with prescalar enabled is 6dB less than the specification. Added a note to On-Chip Temperature Sensor (absolute accuracy) parameter about the averaging calculation. Updated ADC Performance Specifications for Intel® MAX® 10 Single Supply Devices table. Added condition for On-Chip Temperature Sensor (absolute accuracy) parameter: with 64 samples averaging. Updated ADC Performance Specifications for Intel® MAX® 10 Dual Supply Devices table. Updated Digital Supply Voltage minimum value from 1.14 V to 1.15 V and maximum value from 1.26 V to 1.25 V. Updated f_HSCLK and HSIODR specifications for –A7 speed grade in the following tables: True PPDS and Emulated PPDS_E_3R Transmitter Timing Specifications for Intel® MAX® 10 Dual Supply Devices True RSDS and Emulated RSDS_E_3R Transmitter Timing Specifications for Intel® MAX® 10 Dual Supply Devices True Mini-LVDS and Emulated Mini-LVDS_E_3R Transmitter Timing Specifications for Intel® MAX® 10 Dual Supply Devices True LVDS Transmitter Timing Specifications for Intel® MAX® 10 Single Supply Devices True LVDS Transmitter Timing Specifications for Intel® MAX® 10 Dual Supply Devices Emulated LVDS_E_3R Transmitter Timing Specifications for Intel® MAX® 10 Single Supply Devices Emulated LVDS_E_3R, SLVS, and Sub-LVDS Transmitter Timing Specifications for Intel® MAX® 10 Dual Supply Devices LVDS Receiver Timing Specifications for Intel® MAX® 10 Single Supply Devices LVDS, TMDS, HiSpi, SLVS, and Sub-LVDS Receiver Timing Specifications for Intel® MAX® 10 Dual Supply Devices Updated TCCS specifications in the following tables: True PPDS and Emulated PPDS_E_3R Transmitter Timing Specifications for Intel® MAX® 10 Dual Supply Devices True RSDS and Emulated RSDS_E_3R Transmitter Timing Specifications for Intel® MAX® 10 Dual Supply Devices Emulated RSDS_E_1R Transmitter Timing Specifications for Intel® MAX® 10 Dual Supply Devices True Mini-LVDS and Emulated Mini-LVDS_E_3R Transmitter Timing Specifications for Intel® MAX® 10 Dual Supply Devices True LVDS Transmitter Timing Specifications for Intel® MAX® 10 Single Supply Devices True LVDS Transmitter Timing Specifications for Intel® MAX® 10 Dual Supply Devices Emulated LVDS_E_3R Transmitter Timing Specifications for Intel® MAX® 10 Single Supply Devices Emulated LVDS_E_3R, SLVS, and Sub-LVDS Transmitter Timing Specifications for Intel® MAX® 10 Dual Supply Devices Updated t_{x Jitter} specifications in the following tables: True PPDS and Emulated PPDS_E_3R Transmitter Timing Specifications for Intel® MAX® 10 Dual Supply Devices True RSDS and Emulated RSDS_E_3R Transmitter Timing Specifications for Intel® MAX® 10 Dual Supply Devices Emulated RSDS_E_1R Transmitter Timing Specifications for Intel® MAX® 10 Dual Supply Devices True Mini-LVDS and Emulated Mini-LVDS_E_3R Transmitter Timing Specifications for Intel® MAX® 10 Dual Supply Devices True LVDS Transmitter Timing Specifications for Intel® MAX® 10 Dual Supply Devices Emulated LVDS_E_3R, SLVS, and Sub-LVDS Transmitter Timing Specifications for Intel® MAX® 10 Dual Supply Devices Updated SW specifications in LVDS Receiver Timing Specifications for Intel® MAX® 10 Single Supply Devices table. Added a note to t_{x Jitter} for all LVDS tables. Note: TX jitter is the jitter induced from core noise and I/O switching noise. Updated the description for t_LOCK for all LVDS tables: Time required for the PLL to lock, after `CONF_DONE` signal goes high, indicating the completion of device configuration. Updated Memory Output Clock Jitter Specifications section. Updated maximum external memory interfaces frequency from 300 MHz to 303 MHz. Updated PLL output routing from global clock network to PHY clock network. Added I/O Timing for Intel® MAX® 10 Devices table. Added V_HYS in the Glossary table.
January 2015	2015.01.23	Removed a note to V_CCA in Power Supplies Recommended Operating Conditions for Intel® MAX® 10 Dual Supply Devices table. This note is not valid: All V_CCA pins must be connected together for EQFP package. Corrected the maximum value for t_{OUTJITTER_CCJ_ IO} (F_OUT ≥ 100 MHz) from 60 ps to 650 ps in PLL Specifications for Intel® MAX® 10 Devices table.
December 2014	2014.12.15	Restructured Programming/Erasure Specifications for Intel® MAX® 10 Devices table to add temperature specifications that affect the data retention duration. Added statements in the I/O Pin Leakage Current section: Input channel leakage of ADC I/O pins due to hot socket is up to maximum of 1.8 mA. The input channel leakage occurs when the ADC IP core is enabled or disabled. This is applicable to all Intel® MAX® 10 devices with ADC IP core, which are 10M04, 10M08, 10M16, 10M25, 10M40, and 10M50 devices. The ADC I/O pins are in Bank 1A. Added a statement in the I/O Standards Specifications section: You must perform timing closure analysis to determine the maximum achievable frequency for general purpose I/O standards. Updated SSTL-2 Class I and II I/O standard specifications for JEDEC compliance as follows: VIL(AC) Max: Updated from V_REF – 0.35 to V_REF – 0.31 VIH(AC) Min: Updated from V_REF + 0.35 to V_REF + 0.31 Added a note to BLVDS in Differential I/O Standards Specifications for Intel® MAX® 10 Devices table: BLVDS TX is not supported in single supply devices. Added a link to MAX 10 High-Speed LVDS I/O User Guide for the list of I/O standards supported in single supply and dual supply devices. Added a statement in PLL Specifications for Intel® MAX® 10 Single Supply Device table: For V36 package, the PLL specification is based on single supply devices. Added Internal Oscillator Specifications from Intel® MAX® 10 Clocking and PLL User Guide. Added UFM specifications for serial interface. Updated total harmonic distortion (THD) specifications as follows: Single supply devices: Updated from 65 dB to –65 dB Dual supply devices: Updated from 70 dB to –70 dB (updated from 65 dB to –65 dB for dual function pin) Added condition for On-Chip Temperature Sensor—Absolute accuracy parameter in ADC Performance Specifications for Intel® MAX® 10 Dual Supply Devices table. The condition is: with 64 samples averaging. Updated the description in Periphery Performance Specifications to mention that proper timing closure is required in design. Updated HSIODR and f_HSCLK specifications for x10 and x7 modes in True LVDS Transmitter Timing Specifications for Intel® MAX® 10 Dual Supply Devices. Added specifications for low-speed I/O performance pin sampling window in LVDS Receiver Timing Specifications for Intel® MAX® 10 Single Supply Devices table: Max = 900 ps for –C7, –I7, –A7, and –C8 speed grades. Added t_{RU_nCONFIG} and t_{RU_nRSTIMER} specifications for different devices in Remote System Upgrade Circuitry Timing Specifications for Intel® MAX® 10 Devices table. Removed the word "internal oscillator" in User Watchdog Timer Specifications for Intel® MAX® 10 Devices table to avoid confusion. Added IOE programmable delay specifications.
September 2014	2014.09.22	Initial release.