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1. Intel Agilex® 7 F-Series and I-Series General-Purpose I/O Overview
2. Intel Agilex® 7 F-Series and I-Series GPIO Banks
3. Intel Agilex® 7 F-Series and I-Series HPS I/O Banks
4. Intel Agilex® 7 F-Series and I-Series SDM I/O Banks
5. Intel Agilex® 7 F-Series and I-Series I/O Troubleshooting Guidelines
6. Intel Agilex® 7 F-Series and I-Series General-Purpose I/O IPs
7. Programmable I/O Features Description
8. Documentation Related to the Intel Agilex® 7 General-Purpose I/O User Guide: F-Series and I-Series
9. Document Revision History for the Intel Agilex® 7 General-Purpose I/O User Guide: F-Series and I-Series
2.5.1. VREF Sources and VREF Pins
2.5.2. I/O Standards Implementation Based on VCCIO_PIO Voltages
2.5.3. OCT Calibration Block Requirement
2.5.4. I/O Pins Placement Requirements
2.5.5. I/O Standard Selection and I/O Bank Supply Compatibility Check
2.5.6. Simultaneous Switching Noise
2.5.7. Special Pins Requirement
2.5.8. External Memory Interface Pin Placement Requirements
2.5.9. HPS Shared I/O Requirements
2.5.10. Clocking Requirements
2.5.11. SDM Shared I/O Requirements
2.5.12. Unused Pins
2.5.13. Voltage Setting for Unused GPIO Banks
2.5.14. GPIO Pins During Power Sequencing
2.5.15. Drive Strength Requirement for GPIO Input Pins
2.5.16. Maximum DC Current Restrictions
2.5.17. 1.2 V I/O Interface Voltage Level Compatibility
2.5.18. GPIO Pins for the Avalon® Streaming Interface Configuration Scheme
2.5.19. Maximum True Differential Signaling Receiver Pairs Per I/O Lane
6.1.1. Release Information for GPIO Intel® FPGA IP
6.1.2. Generating the GPIO Intel® FPGA IP
6.1.3. GPIO Intel® FPGA IP Parameter Settings
6.1.4. GPIO Intel® FPGA IP Interface Signals
6.1.5. GPIO Intel® FPGA IP Architecture
6.1.6. Verifying Resource Utilization and Design Performance
6.1.7. GPIO Intel® FPGA IP Timing
6.1.8. GPIO Intel® FPGA IP Design Examples
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2.2.1. Supported I/O Standards for GPIO Banks
The VCCIO_PIO and VCCPT power supplies power the GPIO buffers. Each I/O bank has its own VCCIO_PIO power supply and supports only one I/O voltage.
The True Differential Signaling I/O standard is compatible with the LVDS, RSDS, Mini-LVDS, and LVPECL standards at a lower signal swing.
You can place the True Differential Signaling input buffer in a GPIO bank powered by 1.2 V and 1.5 V VCCIO_PIO. The maximum input voltage to the True Differential Signaling input buffer must not exceed the value of :
- For 1.5V VCCIO_PIO bank, the maximum input voltage is 1.7 V
- For 1.2V VCCIO_PIO bank, the maximum input voltage is 1.4 V
By default, the Intel® Quartus® Prime software assigns 1.2 V to the VCCIO_PIO pin in unused I/O banks. To assign 0 V, 1.2 V, or 1.5 V I/O standards to the pin, specify the assignment in the .qsf file located in your design directory.
I/O Standard | VCCIO_PIO (V) | VCCPT (V) | VREF (V) | VTT (V) | JEDEC Standard | |
---|---|---|---|---|---|---|
Input | Output | |||||
1.2 V LVCMOS | 1.2 | 1.2 | 1.8 | — | — | JESD-12A.01 |
SSTL-12 | 1.2 | 1.2 | 1.8 | 0.6 | 0.6 | JESD79-4B |
HSTL-12 | 1.2 | 1.2 | 1.8 | 0.6 | 0.6 | JESD-16A |
HSUL-12 | 1.2 | 1.2 | 1.8 | 0.6 | — | JESD209-3C |
POD12 | 1.2 | 1.2 | 1.8 | Internally calibrated | 1.2 | JESD79-4B |
Differential SSTL-12 1 | 1.2 | 1.2 | 1.8 | — | 0.6 | JESD79-4B |
Differential HSTL-12 1 | 1.2 | 1.2 | 1.8 | — | 0.6 | JESD8-16A |
Differential HSUL-12 1 | 1.2 | 1.2 | 1.8 | — | — | JESD209-3C |
Differential POD-12 1 | 1.2 | 1.2 | 1.8 | Internally calibrated | 1.2 | JESD79-4B |
True Differential Signaling 2 | 1.2/1.5 | 1.5 | 1.8 | — | — | — |
Related Information
1 Uses two single-ended outputs with second output programmed as inverted.
2 True Differential Signaling input buffers are powered by 1.8 V VCCPT