Visible to Intel only — GUID: orz1565749736510
Ixiasoft
Visible to Intel only — GUID: orz1565749736510
Ixiasoft
6.2.4. OCT Intel® FPGA IP Signals
Signal Name | Direction | Description |
---|---|---|
rzqin[n:0] | Input | Input connection from RZQ pad to the OCT block. RZQ pad is connected to an external resistance. The OCT block uses impedance connected to the rzqin port as a reference to generate the calibration code. This signal is available for power-up and user modes. |
calibration_request[n:0] | Input | Set to 1 to request the OCT block to start calibration. Hold the signal for at least 2 ms or until ack_recal is set to 1. This signal is only available for user mode. |
ack_recal[n:0] | Output | When set to 1 indicates OCT block is ready for calibration. There should be no calibration activities from the core to the OCT block until this signal is asserted for every calibration request. This signal is only available for user mode. |
ser_data_n | Output | Transfer serial output calibration data from OCT block to I/O buffer. |