Intel Agilex® 7 General-Purpose I/O User Guide: F-Series and I-Series

Download PDF
ID 683780
Date 2/09/2024
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents
Document Table of Contents x
1. Intel Agilex® 7 F-Series and I-Series General-Purpose I/O Overview 2. Intel Agilex® 7 F-Series and I-Series GPIO Banks 3. Intel Agilex® 7 F-Series and I-Series HPS I/O Banks 4. Intel Agilex® 7 F-Series and I-Series SDM I/O Banks 5. Intel Agilex® 7 F-Series and I-Series I/O Troubleshooting Guidelines 6. Intel Agilex® 7 F-Series and I-Series General-Purpose I/O IPs 7. Programmable I/O Features Description 8. Documentation Related to the Intel Agilex® 7 General-Purpose I/O User Guide: F-Series and I-Series 9. Document Revision History for the Intel Agilex® 7 General-Purpose I/O User Guide: F-Series and I-Series
1. Intel Agilex® 7 F-Series and I-Series General-Purpose I/O Overview x
1.1. Package Selection and I/O Vertical Migration Support 1.2. Types of I/O Banks
2. Intel Agilex® 7 F-Series and I-Series GPIO Banks x
2.1. GPIO Bank Overview 2.2. GPIO Features 2.3. GPIO Implementation Guide 2.4. GPIO Termination 2.5. GPIO Design Guidelines 2.6. GPIO Simulation
2.1. GPIO Bank Overview x
2.1.1. GPIO Bank Structure 2.1.2. GPIO Buffers and Registers
2.2. GPIO Features x
2.2.1. Supported I/O Standards for GPIO Banks 2.2.2. GPIO Buffer Behavior 2.2.3. Programmable I/O Element Features for the GPIO Bank
2.2.3. Programmable I/O Element Features for the GPIO Bank x
2.2.3.1. Guidelines: Programmable Output Slew Rate Control 2.2.3.2. Guidelines: Programmable Open-Drain Output 2.2.3.3. Guidelines: Programmable Bus-Hold 2.2.3.4. Guidelines: Programmable Pull-Up Resistor 2.2.3.5. Guidelines: Programmable De-Emphasis
2.3. GPIO Implementation Guide x
2.3.1. I/O Assignments with the Intel® Quartus® Prime Assignment Editor 2.3.2. Assigning Pin I/O Standards in the Intel® Quartus® Prime Pin Planner
2.3.1. I/O Assignments with the Intel® Quartus® Prime Assignment Editor x
2.3.1.1. Assigning Pin I/O Standards in the Intel® Quartus® Prime Assignment Editor 2.3.1.2. Assigning Programmable IOE Features in the Intel® Quartus® Prime Assignment Editor 2.3.1.3. GPIO Programmable IOE Features Assignment Names and Settings
2.4. GPIO Termination x
2.4.1. Single-Ended I/O Termination in F-Series and I-Series Devices 2.4.2. True Differential Signaling I/O Termination
2.4.1. Single-Ended I/O Termination in F-Series and I-Series Devices x
2.4.1.1. Single-Ended I/O Standard OCT Termination 2.4.1.2. OCT Calibration Block 2.4.1.3. Single-Ended I/O Standards External Termination 2.4.1.4. Single-Ended I/O Termination Implementation Guide
2.4.1.1. Single-Ended I/O Standard OCT Termination x
2.4.1.1.1. RS OCT 2.4.1.1.2. RT OCT 2.4.1.1.3. Dynamic OCT
2.4.1.4. Single-Ended I/O Termination Implementation Guide x
2.4.1.4.1. Configuring OCT Using the Assignment Editor 2.4.1.4.2. OCT Features Assignment Names and Settings
2.4.2. True Differential Signaling I/O Termination x
2.4.2.1. True Differential Signaling I/O Standard OCT Termination 2.4.2.2. True Differential Signaling I/O Standard External Termination
2.4.2.1. True Differential Signaling I/O Standard OCT Termination x
2.4.2.1.1. Configuring Differential Input RD OCT Using the Assignment Editor 2.4.2.1.2. Guidelines: Differential Input RD OCT
2.5. GPIO Design Guidelines x
2.5.1. VREF Sources and VREF Pins 2.5.2. I/O Standards Implementation Based on VCCIO_PIO Voltages 2.5.3. OCT Calibration Block Requirement 2.5.4. I/O Pins Placement Requirements 2.5.5. I/O Standard Selection and I/O Bank Supply Compatibility Check 2.5.6. Simultaneous Switching Noise 2.5.7. Special Pins Requirement 2.5.8. External Memory Interface Pin Placement Requirements 2.5.9. HPS Shared I/O Requirements 2.5.10. Clocking Requirements 2.5.11. SDM Shared I/O Requirements 2.5.12. Unused Pins 2.5.13. Voltage Setting for Unused GPIO Banks 2.5.14. GPIO Pins During Power Sequencing 2.5.15. Drive Strength Requirement for GPIO Input Pins 2.5.16. Maximum DC Current Restrictions 2.5.17. 1.2 V I/O Interface Voltage Level Compatibility 2.5.18. GPIO Pins for the Avalon® Streaming Interface Configuration Scheme 2.5.19. Maximum True Differential Signaling Receiver Pairs Per I/O Lane
2.6. GPIO Simulation x
2.6.1. IBIS Models 2.6.2. HSPICE* Models 2.6.3. Net Length Reports
3. Intel Agilex® 7 F-Series and I-Series HPS I/O Banks x
3.1. HPS I/O Bank Overview 3.2. HPS I/O Features 3.3. HPS I/O Implementation Guide 3.4. HPS I/O Design Guidelines 3.5. HPS I/O Simulation
3.2. HPS I/O Features x
3.2.1. Supported I/O Standards for HPS I/O Banks 3.2.2. HPS I/O Buffer Behavior 3.2.3. Programmable I/O Element Features for the HPS I/O Bank
3.3. HPS I/O Implementation Guide x
3.3.1. Configuring Open Drain Feature for the HPS I/O 3.3.2. I/O Assignments with the Intel® Quartus® Prime Assignment Editor 3.3.3. Assigning Pin I/O Standards in the Intel® Quartus® Prime Pin Planner
3.3.2. I/O Assignments with the Intel® Quartus® Prime Assignment Editor x
3.3.2.1. Assigning Programmable IOE Features in the Intel® Quartus® Prime Assignment Editor 3.3.2.2. HPS I/O Programmable IOE Features Assignment Names and Settings
3.4. HPS I/O Design Guidelines x
3.4.1. Unused Pins 3.4.2. HPS I/O Pins During Power Sequencing 3.4.3. HPS Shared I/O Requirements
3.5. HPS I/O Simulation x
3.5.1. HPS IBIS Models 3.5.2. Net Length Reports
4. Intel Agilex® 7 F-Series and I-Series SDM I/O Banks x
4.1. SDM I/O Bank Overview 4.2. SDM I/O Features 4.3. SDM I/O Design Guidelines 4.4. SDM I/O Simulation
4.2. SDM I/O Features x
4.2.1. Supported I/O Standards for SDM I/O Banks 4.2.2. SDM I/O Buffer Behavior 4.2.3. I/O Standards and Features for Configuration Pins
4.3. SDM I/O Design Guidelines x
4.3.1. Unused Pins 4.3.2. SDM I/O Pins During Power Sequencing
4.4. SDM I/O Simulation x
4.4.1. SDM IBIS Models 4.4.2. Net Length Reports
6. Intel Agilex® 7 F-Series and I-Series General-Purpose I/O IPs x
6.1. GPIO Intel® FPGA IP 6.2. OCT Intel® FPGA IP
6.1. GPIO Intel® FPGA IP x
6.1.1. Release Information for GPIO Intel® FPGA IP 6.1.2. Generating the GPIO Intel® FPGA IP 6.1.3. GPIO Intel® FPGA IP Parameter Settings 6.1.4. GPIO Intel® FPGA IP Interface Signals 6.1.5. GPIO Intel® FPGA IP Architecture 6.1.6. Verifying Resource Utilization and Design Performance 6.1.7. GPIO Intel® FPGA IP Timing 6.1.8. GPIO Intel® FPGA IP Design Examples
6.1.2. Generating the GPIO Intel® FPGA IP x
6.1.2.1. Intel® FPGA IP Generation Output
6.1.3. GPIO Intel® FPGA IP Parameter Settings x
6.1.3.1. Guideline: Swap datain_h and datain_l Ports in Migrated IP
6.1.4. GPIO Intel® FPGA IP Interface Signals x
6.1.4.1. Shared Signals 6.1.4.2. Data Bit-Order for Data Interface 6.1.4.3. Input and Output Bus High and Low Bits 6.1.4.4. Data Interface Signals and Corresponding Clocks
6.1.5. GPIO Intel® FPGA IP Architecture x
6.1.5.1. GPIO Intel® FPGA IP Data Paths 6.1.5.2. Register Packing
6.1.5.1. GPIO Intel® FPGA IP Data Paths x
6.1.5.1.1. Input Path 6.1.5.1.2. Output and Output Enable Paths
6.1.7. GPIO Intel® FPGA IP Timing x
6.1.7.1. Timing Components 6.1.7.2. Delay Elements 6.1.7.3. Timing Analysis 6.1.7.4. Timing Closure Guidelines
6.1.7.3. Timing Analysis x
6.1.7.3.1. Single Data Rate Input Register 6.1.7.3.2. Full-Rate or Half-Rate DDIO Input Register 6.1.7.3.3. Single Data Rate Output Register 6.1.7.3.4. Full-Rate or Half-Rate DDIO Output Register
6.1.8. GPIO Intel® FPGA IP Design Examples x
6.1.8.1. GPIO Intel® FPGA IP Synthesizable Intel® Quartus® Prime Design Example 6.1.8.2. GPIO Intel® FPGA IP Simulation Design Example
6.2. OCT Intel® FPGA IP x
6.2.1. Release Information 6.2.2. Generating the OCT Intel® FPGA IP 6.2.3. OCT Intel® FPGA IP Parameter Settings 6.2.4. OCT Intel® FPGA IP Signals 6.2.5. QSF Assignments 6.2.6. OCT Intel® FPGA IP Architecture 6.2.7. OCT Intel® FPGA IP Design Example
6.2.2. Generating the OCT Intel® FPGA IP x
6.2.2.1. Intel® FPGA IP Generation Output
6.2.7. OCT Intel® FPGA IP Design Example x
6.2.7.1. Generating the Intel® Quartus® Prime Design Example
7. Programmable I/O Features Description x
7.1. Programmable Pre-Emphasis 7.2. Programmable De-Emphasis 7.3. Programmable Differential Output Voltage
1. Intel Agilex® 7 F-Series and I-Series General-Purpose I/O Overview
2. Intel Agilex® 7 F-Series and I-Series GPIO Banks
3. Intel Agilex® 7 F-Series and I-Series HPS I/O Banks
4. Intel Agilex® 7 F-Series and I-Series SDM I/O Banks
5. Intel Agilex® 7 F-Series and I-Series I/O Troubleshooting Guidelines
6. Intel Agilex® 7 F-Series and I-Series General-Purpose I/O IPs
7. Programmable I/O Features Description
8. Documentation Related to the Intel Agilex® 7 General-Purpose I/O User Guide: F-Series and I-Series
9. Document Revision History for the Intel Agilex® 7 General-Purpose I/O User Guide: F-Series and I-Series

6.1.3. GPIO Intel® FPGA IP Parameter Settings

You can set the parameter settings for the GPIO IP in the Intel® Quartus® Prime software. There are three groups of options: General, Buffer, and Registers.
Table 41.   GPIO IP Parameters—General
Parameter Condition Allowed Values Description
Data Direction —
  • Input
  • Output
  • Bidir

Specifies the data direction for the GPIO.

Data width —

1 to 128

Specifies the data width.

Use legacy top-level port names —
  • On
  • Off

Use same port names as in Stratix® V, Arria® V, and Cyclone® V devices.

For example, dout becomes dataout_h and dataout_l, and din becomes datain_h and datain_l.

Note: The behavior of these ports are different than in the Stratix® V, Arria® V, and Cyclone® V devices. For the migration guideline, refer to the related information.
Table 42.   GPIO IP Parameters—Buffer
Parameter Condition Allowed Values Description
Use differential buffer —
  • On
  • Off

If turned on, enables differential I/O buffers.

Use pseudo differential buffer
  • Data Direction = Output
  • Use differential buffer = On
  • On
  • Off

If turned on in output mode, enables pseudo differential output buffers.

This option is automatically turned on for bidirectional mode if you turn on Use differential buffer.

Use bus-hold circuitry
  • Data Direction = Input or Bidir
  • Use differential buffer = Off
  • On
  • Off

If turned on, the bus hold circuitry can weakly hold the signal on an I/O pin at its last-driven state where the output buffer state is 1 or 0 but not high-impedance.

Use open drain output
  • Data Direction = Output or Bidir
  • Use differential buffer = Off
  • On
  • Off

If turned on, the open drain output enables the device to provide system-level control signals such as interrupt and write enable signals that can be asserted by multiple devices in your system.

Enable output enable port Data Direction = Output
  • On
  • Off

If turned on, enables user input to the OE port. This option is automatically turned on for bidirectional mode.

Enable seriestermination/ paralleltermination ports —
  • On
  • Off

If turned on, enables the terminationcontrol port of the output buffer to allow user-mode OCT calibration.

Table 43.   GPIO IP Parameters—Registers
Parameter Condition Allowed Values Description
Register mode —
  • None
  • Simple register
  • DDIO

Specifies the register mode for the GPIO IP:

  • None—specifies a simple wire connection from/to the buffer.
  • Simple register—specifies that the DDIO is used as a simple register in single data-rate mode (SDR). The Fitter may pack this register in the I/O.
  • DDIO— specifies that the IP core uses the DDIO.
Enable synchronous clear / preset port Register mode = DDIO
  • None
  • Clear
  • Preset

Specifies how to implement synchronous reset port.

  • None—Disables synchronous reset port.
  • Clear—Enables the SCLR port for synchronous clears.
  • Preset—Enables the SSET port for synchronous preset.
Enable asynchronous clear / preset port Register mode = DDIO
  • None
  • Clear
  • Preset

Specifies how to implement asynchronous reset port.

  • None—Disables asynchronous reset port.
  • Clear—Enables the ACLR port for asynchronous clears.
  • Preset—Enables the ASET port for asynchronous preset.

ACLR and ASET signals are active high.

Enable clock enable ports Register mode = DDIO
  • On
  • Off
  • On—exposes the clock enable (CKE) port to allow you to control when data is clocked in or out. This signal prevents data from being passed through without your control.
  • Off—clock enable port is not exposed and data always pass through the register automatically.
Half Rate logic Register mode = DDIO
  • On
  • Off
 If turned on, enables half-rate DDIO.
Separate input/output Clocks
  • Data Direction = Bidir
  • Register mode = Simple register or DDIO
  • On
  • Off
 If turned on, enables separate clocks (CK_IN and CK_OUT) for the input and output paths in bidirectional mode.

Section Content
Guideline: Swap datain_h and datain_l Ports in Migrated IP

Related Information
Level Two Title