Intel® Quartus® Prime Pro Edition User Guide: PCB Design Tools

Download PDF
ID 683768
Date 11/04/2020
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents
Document Table of Contents x
1. Signal Integrity Analysis with Third-Party Tools 2. Reviewing Printed Circuit Board Schematics with the Intel® Quartus® Prime Software 3. Mentor Graphics* PCB Design Tools Support 4. Cadence Board Design Tools Support 5. Intel Quartus Prime Pro Edition User Guide: PCB Design Tools Document Archives A. Intel® Quartus® Prime Pro Edition User Guides
1. Signal Integrity Analysis with Third-Party Tools x
1.1. Signal Integrity Analysis with Third-Party Tools 1.2. I/O Model Selection: IBIS or HSPICE 1.3. FPGA to Board Signal Integrity Analysis Flow 1.4. Simulation with IBIS Models 1.5. Simulation with HSPICE Models 1.6. Signal Integrity Analysis with Third-Party Tools Document Revision History
1.1. Signal Integrity Analysis with Third-Party Tools x
1.1.1. Signal Integrity Simulations with HSPICE and IBIS Models
1.3. FPGA to Board Signal Integrity Analysis Flow x
1.3.1. Create I/O and Board Trace Model Assignments 1.3.2. Output File Generation 1.3.3. Customize the Output Files 1.3.4. Set Up and Run Simulations in Third-Party Tools 1.3.5. Interpret Simulation Results
1.4. Simulation with IBIS Models x
1.4.1. Elements of an IBIS Model 1.4.2. Creating Accurate IBIS Models 1.4.3. Design Simulation Using the Mentor Graphics* HyperLynx* Software 1.4.4. Configuring LineSim to Use Intel IBIS Models 1.4.5. Integrating Intel IBIS Models into LineSim Simulations 1.4.6. Running and Interpreting LineSim Simulations
1.4.2. Creating Accurate IBIS Models x
1.4.2.1. Download IBIS Models 1.4.2.2. Generate Custom IBIS Models with the IBIS Writer
1.5. Simulation with HSPICE Models x
1.5.1. Supported Devices and Signaling 1.5.2. Accessing HSPICE Simulation Kits 1.5.3. The Double Counting Problem in HSPICE Simulations 1.5.4. HSPICE Writer Tool Flow 1.5.5. Running an HSPICE Simulation 1.5.6. Interpreting the Results of an Output Simulation 1.5.7. Interpreting the Results of an Input Simulation 1.5.8. Viewing and Interpreting Tabular Simulation Results 1.5.9. Viewing Graphical Simulation Results 1.5.10. Making Design Adjustments Based on HSPICE Simulations 1.5.11. Sample Input for I/O HSPICE Simulation Deck 1.5.12. Sample Output for I/O HSPICE Simulation Deck 1.5.13. Advanced Topics
1.5.3. The Double Counting Problem in HSPICE Simulations x
1.5.3.1. Defining the Double Counting Problem 1.5.3.2. The Solution to Double Counting
1.5.4. HSPICE Writer Tool Flow x
1.5.4.1. Applying I/O Assignments 1.5.4.2. Enabling HSPICE Writer 1.5.4.3. Enabling HSPICE Writer Using Assignments 1.5.4.4. Naming Conventions for HSPICE Files 1.5.4.5. Invoking HSPICE Writer 1.5.4.6. Invoking HSPICE Writer from the Command Line 1.5.4.7. Customizing Automatically Generated HSPICE Decks
1.5.11. Sample Input for I/O HSPICE Simulation Deck x
1.5.11.1. Header Comment 1.5.11.2. Simulation Conditions 1.5.11.3. Simulation Options 1.5.11.4. Constant Definition 1.5.11.5. Buffer Netlist 1.5.11.6. Drive Strength 1.5.11.7. I/O Buffer Instantiation 1.5.11.8. Board Trace and Termination 1.5.11.9. Stimulus Model 1.5.11.10. Simulation Analysis
1.5.12. Sample Output for I/O HSPICE Simulation Deck x
1.5.12.1. Header Comment 1.5.12.2. Simulation Conditions 1.5.12.3. Simulation Options 1.5.12.4. Constant Definition 1.5.12.5. I/O Buffer Netlist 1.5.12.6. Drive Strength 1.5.12.7. Slew Rate and Delay Chain 1.5.12.8. I/O Buffer Instantiation 1.5.12.9. Board and Trace Termination 1.5.12.10. Double-Counting Compensation Circuitry 1.5.12.11. Simulation Analysis
1.5.13. Advanced Topics x
1.5.13.1. PVT Simulations 1.5.13.2. Hold Time Analysis 1.5.13.3. I/O Voltage Variations 1.5.13.4. Correlation Report
2. Reviewing Printed Circuit Board Schematics with the Intel® Quartus® Prime Software x
2.1. Reviewing Intel® Quartus® Prime Software Settings 2.2. Reviewing Device Pin-Out Information in the Fitter Report 2.3. Reviewing Compilation Error and Warning Messages 2.4. Using Additional Intel® Quartus® Prime Software Features 2.5. Using Additional Intel® Quartus® Prime Software Tools 2.6. Reviewing Printed Circuit Board Schematics with the Intel® Quartus® Prime Software Revision History
2.1. Reviewing Intel® Quartus® Prime Software Settings x
2.1.1. Device and Pins Options Dialog Box Settings
2.1.1. Device and Pins Options Dialog Box Settings x
2.1.1.1. Configuration Settings 2.1.1.2. Unused Pin Settings 2.1.1.3. Dual-Purpose Pins Settings 2.1.1.4. Voltage Settings 2.1.1.5. Error Detection CRC Settings
2.5. Using Additional Intel® Quartus® Prime Software Tools x
2.5.1. Pin Planner
3. Mentor Graphics* PCB Design Tools Support x
3.1. Integrating with DxDesigner 3.2. Mentor Graphics* PCB Design Tools Support Revision History
3.1. Integrating with DxDesigner x
3.1.1. DxDesigner Project Settings 3.1.2. Creating Schematic Symbols in DxDesigner
4. Cadence Board Design Tools Support x
4.1. Cadence PCB Design Tools Support 4.2. Product Comparison 4.3. FPGA-to-PCB Design Flow 4.4. Setting Up the Intel® Quartus® Prime Software 4.5. FPGA-to-Board Integration with the Cadence Allegro Design Entry HDL Software 4.6. FPGA-to-Board Integration with Cadence Allegro Design Entry CIS Software 4.7. Cadence Board Design Tools Support Revision History
4.3. FPGA-to-PCB Design Flow x
4.3.1. Integrating Intel FPGA Designs
4.4. Setting Up the Intel® Quartus® Prime Software x
4.4.1. Generating a .pin File
4.5. FPGA-to-Board Integration with the Cadence Allegro Design Entry HDL Software x
4.5.1. Creating Symbols 4.5.2. Instantiating the Symbol in the Cadence Allegro Design Entry HDL Software
4.5.1. Creating Symbols x
4.5.1.1. Cadence Allegro PCB Librarian Part Developer Tool
4.5.1.1. Cadence Allegro PCB Librarian Part Developer Tool x
4.5.1.1.1. Cadence Allegro PCB Librarian Part Developer Tool in the Design Flow 4.5.1.1.2. Import and Export Wizard 4.5.1.1.3. Editing and Fracturing Symbol 4.5.1.1.4. Updating FPGA Symbols
4.6. FPGA-to-Board Integration with Cadence Allegro Design Entry CIS Software x
4.6.1. Creating a Cadence Allegro Design Entry CIS Project 4.6.2. Generating a Part 4.6.3. Generating Schematic Symbol 4.6.4. Splitting a Part 4.6.5. Instantiating a Symbol in a Design Entry CIS Schematic 4.6.6. Intel Libraries for the Cadence Allegro Design Entry CIS Software
4.6.6. Intel Libraries for the Cadence Allegro Design Entry CIS Software x
4.6.6.1. Using the Intel-provided Libraries with your Cadence Allegro Design Entry CIS Project
1. Signal Integrity Analysis with Third-Party Tools
2. Reviewing Printed Circuit Board Schematics with the Intel® Quartus® Prime Software
3. Mentor Graphics* PCB Design Tools Support
4. Cadence Board Design Tools Support
5. Intel Quartus Prime Pro Edition User Guide: PCB Design Tools Document Archives
A. Intel® Quartus® Prime Pro Edition User Guides

4.5.1.1.3. Editing and Fracturing Symbol

After creating your new symbol in the Cadence Allegro PCB Librarian Part Developer tool, you can edit the symbol graphics, fracture the symbol into multiple slots, and add or change package or symbol properties.

The Part Developer Symbol Editor contains many graphical tools to edit the graphics of a particular symbol. To edit the symbol graphics, select the symbol in the cell hierarchy. The Symbol Pins tab appears. You can edit the preview graphic of the symbol in the Symbol Pins tab.

Fracturing a Cadence Allegro PCB Librarian Part Developer package into separate symbol slots is useful for FPGA designs. A single symbol for most FPGA packages might be too large for a single schematic page. Splitting the part into separate slots allows you to organize parts of the symbol by function, creating cleaner circuit schematics. For example, you can create one slot for an I/O symbol, a second slot for a JTAG symbol, and a third slot for a power/ground symbol.

Figure 20. Splitting a Symbol into Multiple Slots


To fracture a part into separate slots, or to modify the slot locations of pins on parts fractured in the Cadence Allegro PCB Librarian Part Developer tool, follow these steps:

  1. Start the Cadence Allegro Design Project Manager.
  2. On the Flows menu, click Library Management.
  3. Click Part Developer.
  4. Click the name of the package you want to change in the cell hierarchy.
  5. Click Functions/Slots. If you are not creating new slots but want to change the slot location of some pins, proceed to Step 6. If you are creating new slots, click Add. A dialog box appears, allowing you to add extra symbol slots. Set the number of extra slots you want to add to the existing symbol, not the total number of desired slots for the part. Click OK.
  6. Click Distribute Pins. Specify the slot location for each pin. Use the checkboxes in each column to move pins from one slot to another. Click OK.
  7. After distributing the pins, click the Package Pin tab and click Generate Symbol(s).
  8. Select whether to create a new symbol or modify an existing symbol in each slot. Click OK.

    The newly generated or modified slot symbols appear as separate symbols in the cell hierarchy. Each of these symbols can be edited individually.

    CAUTION:
    The Cadence Allegro PCB Librarian Part Developer tool allows you to remap pin assignments in the Package Pin tab of the main Cadence Allegro PCB Librarian Part Developer window. If signals remap to different pins in the Cadence Allegro PCB Librarian Part Developer tool, the changes reflect only in regenerated symbols for use in your schematics. You cannot transfer pin assignment changes to the Intel® Quartus® Prime software from the Cadence Allegro PCB Librarian Part Developer tool, which creates a potential mismatch of the schematic symbols and assignments in the FPGA design. If pin assignment changes are necessary, make the changes in the Intel® Quartus® Prime Pin Planner instead of the Cadence Allegro PCB Librarian Part Developer tool, and update the symbol as described in the following sections.

    For more information about creating, editing, and organizing component symbols with the Cadence Allegro PCB Librarian Part Developer tool, refer to the Part Developer Help.

Level Two Title