Intel® Quartus® Prime Pro Edition User Guide: PCB Design Tools

Download PDF
ID 683768
Date 11/04/2020
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents
Document Table of Contents x
1. Signal Integrity Analysis with Third-Party Tools 2. Reviewing Printed Circuit Board Schematics with the Intel® Quartus® Prime Software 3. Mentor Graphics* PCB Design Tools Support 4. Cadence Board Design Tools Support 5. Intel Quartus Prime Pro Edition User Guide: PCB Design Tools Document Archives A. Intel® Quartus® Prime Pro Edition User Guides
1. Signal Integrity Analysis with Third-Party Tools x
1.1. Signal Integrity Analysis with Third-Party Tools 1.2. I/O Model Selection: IBIS or HSPICE 1.3. FPGA to Board Signal Integrity Analysis Flow 1.4. Simulation with IBIS Models 1.5. Simulation with HSPICE Models 1.6. Signal Integrity Analysis with Third-Party Tools Document Revision History
1.1. Signal Integrity Analysis with Third-Party Tools x
1.1.1. Signal Integrity Simulations with HSPICE and IBIS Models
1.3. FPGA to Board Signal Integrity Analysis Flow x
1.3.1. Create I/O and Board Trace Model Assignments 1.3.2. Output File Generation 1.3.3. Customize the Output Files 1.3.4. Set Up and Run Simulations in Third-Party Tools 1.3.5. Interpret Simulation Results
1.4. Simulation with IBIS Models x
1.4.1. Elements of an IBIS Model 1.4.2. Creating Accurate IBIS Models 1.4.3. Design Simulation Using the Mentor Graphics* HyperLynx* Software 1.4.4. Configuring LineSim to Use Intel IBIS Models 1.4.5. Integrating Intel IBIS Models into LineSim Simulations 1.4.6. Running and Interpreting LineSim Simulations
1.4.2. Creating Accurate IBIS Models x
1.4.2.1. Download IBIS Models 1.4.2.2. Generate Custom IBIS Models with the IBIS Writer
1.5. Simulation with HSPICE Models x
1.5.1. Supported Devices and Signaling 1.5.2. Accessing HSPICE Simulation Kits 1.5.3. The Double Counting Problem in HSPICE Simulations 1.5.4. HSPICE Writer Tool Flow 1.5.5. Running an HSPICE Simulation 1.5.6. Interpreting the Results of an Output Simulation 1.5.7. Interpreting the Results of an Input Simulation 1.5.8. Viewing and Interpreting Tabular Simulation Results 1.5.9. Viewing Graphical Simulation Results 1.5.10. Making Design Adjustments Based on HSPICE Simulations 1.5.11. Sample Input for I/O HSPICE Simulation Deck 1.5.12. Sample Output for I/O HSPICE Simulation Deck 1.5.13. Advanced Topics
1.5.3. The Double Counting Problem in HSPICE Simulations x
1.5.3.1. Defining the Double Counting Problem 1.5.3.2. The Solution to Double Counting
1.5.4. HSPICE Writer Tool Flow x
1.5.4.1. Applying I/O Assignments 1.5.4.2. Enabling HSPICE Writer 1.5.4.3. Enabling HSPICE Writer Using Assignments 1.5.4.4. Naming Conventions for HSPICE Files 1.5.4.5. Invoking HSPICE Writer 1.5.4.6. Invoking HSPICE Writer from the Command Line 1.5.4.7. Customizing Automatically Generated HSPICE Decks
1.5.11. Sample Input for I/O HSPICE Simulation Deck x
1.5.11.1. Header Comment 1.5.11.2. Simulation Conditions 1.5.11.3. Simulation Options 1.5.11.4. Constant Definition 1.5.11.5. Buffer Netlist 1.5.11.6. Drive Strength 1.5.11.7. I/O Buffer Instantiation 1.5.11.8. Board Trace and Termination 1.5.11.9. Stimulus Model 1.5.11.10. Simulation Analysis
1.5.12. Sample Output for I/O HSPICE Simulation Deck x
1.5.12.1. Header Comment 1.5.12.2. Simulation Conditions 1.5.12.3. Simulation Options 1.5.12.4. Constant Definition 1.5.12.5. I/O Buffer Netlist 1.5.12.6. Drive Strength 1.5.12.7. Slew Rate and Delay Chain 1.5.12.8. I/O Buffer Instantiation 1.5.12.9. Board and Trace Termination 1.5.12.10. Double-Counting Compensation Circuitry 1.5.12.11. Simulation Analysis
1.5.13. Advanced Topics x
1.5.13.1. PVT Simulations 1.5.13.2. Hold Time Analysis 1.5.13.3. I/O Voltage Variations 1.5.13.4. Correlation Report
2. Reviewing Printed Circuit Board Schematics with the Intel® Quartus® Prime Software x
2.1. Reviewing Intel® Quartus® Prime Software Settings 2.2. Reviewing Device Pin-Out Information in the Fitter Report 2.3. Reviewing Compilation Error and Warning Messages 2.4. Using Additional Intel® Quartus® Prime Software Features 2.5. Using Additional Intel® Quartus® Prime Software Tools 2.6. Reviewing Printed Circuit Board Schematics with the Intel® Quartus® Prime Software Revision History
2.1. Reviewing Intel® Quartus® Prime Software Settings x
2.1.1. Device and Pins Options Dialog Box Settings
2.1.1. Device and Pins Options Dialog Box Settings x
2.1.1.1. Configuration Settings 2.1.1.2. Unused Pin Settings 2.1.1.3. Dual-Purpose Pins Settings 2.1.1.4. Voltage Settings 2.1.1.5. Error Detection CRC Settings
2.5. Using Additional Intel® Quartus® Prime Software Tools x
2.5.1. Pin Planner
3. Mentor Graphics* PCB Design Tools Support x
3.1. Integrating with DxDesigner 3.2. Mentor Graphics* PCB Design Tools Support Revision History
3.1. Integrating with DxDesigner x
3.1.1. DxDesigner Project Settings 3.1.2. Creating Schematic Symbols in DxDesigner
4. Cadence Board Design Tools Support x
4.1. Cadence PCB Design Tools Support 4.2. Product Comparison 4.3. FPGA-to-PCB Design Flow 4.4. Setting Up the Intel® Quartus® Prime Software 4.5. FPGA-to-Board Integration with the Cadence Allegro Design Entry HDL Software 4.6. FPGA-to-Board Integration with Cadence Allegro Design Entry CIS Software 4.7. Cadence Board Design Tools Support Revision History
4.3. FPGA-to-PCB Design Flow x
4.3.1. Integrating Intel FPGA Designs
4.4. Setting Up the Intel® Quartus® Prime Software x
4.4.1. Generating a .pin File
4.5. FPGA-to-Board Integration with the Cadence Allegro Design Entry HDL Software x
4.5.1. Creating Symbols 4.5.2. Instantiating the Symbol in the Cadence Allegro Design Entry HDL Software
4.5.1. Creating Symbols x
4.5.1.1. Cadence Allegro PCB Librarian Part Developer Tool
4.5.1.1. Cadence Allegro PCB Librarian Part Developer Tool x
4.5.1.1.1. Cadence Allegro PCB Librarian Part Developer Tool in the Design Flow 4.5.1.1.2. Import and Export Wizard 4.5.1.1.3. Editing and Fracturing Symbol 4.5.1.1.4. Updating FPGA Symbols
4.6. FPGA-to-Board Integration with Cadence Allegro Design Entry CIS Software x
4.6.1. Creating a Cadence Allegro Design Entry CIS Project 4.6.2. Generating a Part 4.6.3. Generating Schematic Symbol 4.6.4. Splitting a Part 4.6.5. Instantiating a Symbol in a Design Entry CIS Schematic 4.6.6. Intel Libraries for the Cadence Allegro Design Entry CIS Software
4.6.6. Intel Libraries for the Cadence Allegro Design Entry CIS Software x
4.6.6.1. Using the Intel-provided Libraries with your Cadence Allegro Design Entry CIS Project
1. Signal Integrity Analysis with Third-Party Tools
2. Reviewing Printed Circuit Board Schematics with the Intel® Quartus® Prime Software
3. Mentor Graphics* PCB Design Tools Support
4. Cadence Board Design Tools Support
5. Intel Quartus Prime Pro Edition User Guide: PCB Design Tools Document Archives
A. Intel® Quartus® Prime Pro Edition User Guides

1.4.3. Design Simulation Using the Mentor Graphics* HyperLynx* Software

You must integrate IBIS models downloaded from the Intel website or created with the Intel® Quartus® Prime IBIS Writer into board design simulations to accurately model timing and signal integrity.

The HyperLynx* software from Mentor Graphics* is one of the most popular tools for design simulation. The HyperLynx* software makes it easy to integrate IBIS models into simulations.

The HyperLynx* software is a PCB analysis and simulation tool for high-speed designs, consisting of two products, LineSim and BoardSim.

LineSim is an early simulation tool. Before any board routing takes place, you use LineSim to simulate “what if” scenarios that assist in creating routing rules and defining board parameters.

BoardSim is a post-layout tool that you use to analyze existing board routing. You select one or more nets from a board layout file and BoardSim simulates those nets in a manner similar to LineSim. With board and routing parameters, and surrounding signal routing known, highly accurate simulations of the final fabricated PCB are possible.

This section focuses on LineSim. Because the process of creating and running simulations is very similar for both LineSim and BoardSim, the details of IBIS model use in LineSim applies to simulations in BoardSim.

You configure simulations in LineSim using a schematic GUI to create connections and topologies between I/O buffers, route trace segments, and termination components. LineSim provides two methods for creating routing schematics: cell-based and free-form. Cell-based schematics are based on fixed cells consisting of typical placements of buffers, trace impedances, and components. Parts of the grid-based cells are filled with the desired objects to create the topology. A topology in a cell-based schematic is limited by the available connections within and between the cells.

A more robust and expandable way to create a circuit schematic for simulation is to use the free-form schematic format in LineSim. The free-form schematic format makes it easy to place parts into any configuration and edit them as required. This section describes the use of IBIS models with free-form schematics, but the process is nearly identical for cell-based schematics.

Figure 3. HyperLynx LineSim Free-Form Schematic Editor

When you use HyperLynx* software to perform simulations, you typically perform the following steps:

  1. Create a new LineSim free-form schematic document and set up the board stackup for your PCB using the Stackup Editor. In this editor, specify board layer properties including layer thickness, dielectric constant, and trace width.
  2. Create a circuit schematic for the net you want to simulate. The schematic represents all the parts of the routed net including source and destination I/O buffers, termination components, transmission line segments, and representations of impedance discontinuities such as vias or connectors.
  3. Assign IBIS models to the source and destination I/O buffers to represent their behavior during operation.
  4. Attach probes from the digital oscilloscope that is built in to LineSim to points in the circuit that you want to monitor during simulation. Typically, at least one probe is attached to the pin of a destination I/O buffer. For differential signals, you can attach a differential probe to both the positive and negative pins at the destination.
  5. Configure and run the simulation. You can simulate a rising or falling edge and test the circuit under different drive strength conditions.
  6. Interpret the results and make adjustments. Based on the waveforms captured in the digital oscilloscope, you can adjust anything in the circuit schematic to correct any signal integrity issues, such as overshoot or ringing. If necessary, you can make I/O assignment changes in the Intel® Quartus® Prime software, regenerate the IBIS file with the IBIS Writer, and apply the updated IBIS model to the buffers in your HyperLynx* software schematic.
  7. Repeat the simulations and circuit adjustments until you are satisfied with the results.
  8. When the operation of the net meets your design requirements, implement changes to your I/O assignments in the Intel® Quartus® Prime software and optionally adjust your board routing constraints, component values, and placement to match the simulation.
For more information about HyperLynx* software, including schematic creation, simulation setup, model usage, product support, licensing, and training, refer to the Mentor Graphics* webpage.
Related Information
Level Two Title